Center for VLSI Design
THE CONCEPT OF CVD
The CVD day to day operation is overseen by the Bachelor and Masters Students of electronics and communication engineering. The center focuses specifically on Digital, Analog, Mixed-signal and SOC VLSI design. Its faculty members bring extensive academic experience and broad industrial experience. The center also leans heavily on professional interactions with industry for guidance and support.
The CVD operates 24/7 to have an effective transfer of knowledge from post graduates to undergraduates. Each Undergraduate is paired with Postgraduate. The advantage of this mechanism is that Undergraduates get a mentor. It also raises the bar of the Undergraduates making them enthusiastic to learn above and beyond the Syllabus and developing a genuine love for the subject which makes these students more successful. This healthy Echo system results in quality project works and paper publication.
|EDA TOOL INFRASTRUCTURE||HARDWARE INFRASTRUCTURE|
Cadence/Synopsys University Bundle Full Suite
SOC Zynq 7000 Development Boards
AREA OF FOCUS
- Ultra Low Power Biomedical IC Design
- Embedded Systems with FPGA
- Compact Modeling of Emerging nano Scale Devices: NEMS, FINFETS, TFETS
- Image Processing-Segmentation, Edge Detection
- VLSI Solutions for Residue Number System, Reversible Logic
- Low Power VLSI Designs
- VLSI Signal Processing
|Digital Design Using Verilog||CMOS Circuit Design and Layout|
STUDENT PROJECTS 2015
DIGITAL CIRCUIT DESIGN
- Design and Implementation of Residue Number System
- Power and area Efficient Forward/Reverse convertor Architectures using Cadence RTL Compiler
- Power and area Efficient Generic and Special Residue Adders and Multiplier Architectures using Cadence RTL Compiler
- Design and Analysis of High Speed Computer Arithmetic’s
- Power and area Efficient CLA Adder, Parallel Prefix adder Architectures using cadence RTL Compiler
- Power and area Efficient Compressor Architectures using Cadence RTL compiler
- Design and analysis of communication Protocols
- HDLC, I2C protocols using Xilinx tools
- AMBHA protocols using Xilinx tools
- Design of Signal/Image processing Algorithms
- Skin Tone Processor using Xilinx tools
- Edge Detection Algorithms using Xilinx system generator
ANALOG CIRCUIT DESIGN
- Power Reduction Techniques in CMOS Analog/ Digital Circuits
- Design and analysis of Flip Flop’s Using Lector logic using Cadence Virtuoso SE.
- Analysis of Variable Threshold In MOSFET Logics .
- Carry Propagate Adder using MTCMOS logic using Cadence Virtuoso SE.
- Design and analysis of OTA logic using Cadence Virtuoso SE
- analysis of 3 stage Operational Amplifiers using Cadence Virtuoso SE.
- Analysis of Clock feed through problems in analog circuits.
- PVT corner Analysis of Operational Amplifiers.
TRAINING PROGRAMS & ACTIVITIES
- National Level Workshop on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC”
- VLSI Foundation Course” conducted by CYIENT
- Add-On Course on “Digital Design with FPGA” Organized in collaboration with Dr. Vijay Krishnan Narayanan, Prof, Penn state university, USA and Dr. Kevin, Research Associate, PSU, USA.
- FDP on ” Analog Circuit Design using Cadence Tools”
- Workshop on “VLSI Design” by Mr.Brad Fross,Xilinx, USA
- 6-Months Add-on Course on “VLSI Design” by Seer academy.
- Prof Das Gupta from IIT, Roorkee : “Latest Research trends in emerging nano scale Solid State Device Technologies”.
- Mr. Srikanth Jadcherla, Synopsys, USA :“Low power Trends in VLSI Design”
- Mr.Yatin Trivedi, Synopsys, USA: “VLSI Carriers & the Role of Standardization in the Industry”.
- Mr.Srikanth Jadcherla, Synopsys, USA: “Low Power trends in VLSI Design” .
- Dr.M.Manikanden, professor, Anna university: “VLSI Technology”.
MAJOR PUBLICATIONS & DESIGN CONTESTS
- 26th International Conference on VLSI, Pune: Energy Efficient and Robust SRAM Design with co design of alternative bit cells topologies and Memory Architectures”2013.
- 25th International Conference on VLSI, Hyderabad: Design and Implementation of PCI Target device Core with single interface modeling using SEAD 90nm, 2012.
- Cadence Design Contest: Design and implementation of efficient special modulo Adder, 2014.
- IEEE International Conference On Devices Circuits And Systems: Residue Arithmetic’s Using Reversible Logic Gates, 2014.
- IEEE International Conference On Devices Circuits And Systems: Ultra-Low Power Circuit Design using Double-Gate FinFETs, 2014.
- IEEE-Prime Asia: Enhanced bias –flip rectifier with ultra- low power control for piezo electric energy harvester in the microwatt application scenario, 2012.
- IEEE-International Conference on Communications, Devices and Intelligent Systems: A Novel approach and Implementation of Robot path planning using parallel processing algorithm, 2012.
- IEEE-International Conference on Electrical, Electronics, Signals, Communication and Optimization, Prime Asia : A High speed and area efficient booth recorded Wallace tree multiplier for arithmetic circuits, 2012.
- IEEE-Prime Asia: Variable input delay CMOS logic for dynamic IR drop reduction, 2012.