B V Raju Institute of Technology

Vishnupur, Narsapur, Medak (Dist), Telangana

(UGC Autonomous)

CENTER FOR VLSI DESIGN (CVD)

About CVD

The Electronics and Communication Engineering established the Center for VLSI Design (CVD) in 2008. The CVD focuses specifically on Digital ASIC design, Analog and Mixed-signal and SOC VLSI design. The Objective of this center is to create an academic center of excellence in semiconductor technologies such as RTL, verification, physical design, DFT and Analog layouts. The key activities of the above center is to provide domain training by VLSI experts from Industry to Undergraduate and Post-Graduate students supported by CVD faculty members. The center also leans heavily on professional interactions with industry for guidance and support. The CVD associated with few VLSI companies like SYNOPSYS, XILIX, CYIENT, ADEPTCHIPS, MANJEERA DIGITAL SYSTEMS and HYSOC etc to provide training to the UG/PG students in VLSI domain. More than 140 students got placed in VLSI companies during the last six years.

We welcome the industries to collaboration for the benefit of our faculty and students; and also to bridge the gap between the Industry and Academia. This will surely be helpful for our students to choose their future career in the core Industry. 

Coordinator: Mr.U Gnaneshwara Chary

Faculty Members:      

Dr. K Madhava Rao

Dr. Pavan Kumar Bikki

Mr. C Ramesh Kumar Reddy

Mrs. Ch. Vandana

Mr. K Charan Kumar

Objectives

• To Full fill the VLSI Industry-Academia Gap
• Hands on expose on ASIC and FPGA tools which includes Analog Design and Layout also.
• Final goal of CVD is to develop an Integrated circuit (IC) from BVRIT.

LIST OF SYNOPSYS EDA TOOLS

Training activities

• Industrial Digital Design with Verilog HDL
• Verification using System Verilog
• Synthesis and STA
• Design for testability
• Physical Design
• CMOS Digital, Analog & Mixed Signal Design
• Linux & TCL Scripting

Industrial Interactions and Outcomes:                          

CVD-Workshops

VLSI core Internships and placements:

2021-22

2020-21

2019-20

2018-19

2017-18

2016-17

Memorandum of Understanding MOU’S:

Paper publications:

Publications (2022-23):

Udari GnaneshwaraChary,, and Kakarla Hari Kishore. “Low Voltage and Low Power Front Panel Design for 12 Lead ECG.” IEEE Access 10 (2022): 69455-69461.

U.Gnaneshwara chary, et al. “Area Optimised Efficient Multiplication Using Modified Round Square Approximation.” 2023 IEEE International Conference on Integrated Circuits and Communication Systems (ICICACS). IEEE, 2023.(Best Paper award)

Udari Gnaneshwara chary et al. “Performance of a Low-Power 6T-SRAM Cell for Energy-Efficient Leakage Reduction Using DTMOS Technique.” Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems: ICCCES 2022. Singapore: Springer Nature Singapore, 2023.

Madhava Rao, K., Santhosh Kumar, V., Hindumathi, V.Energy Efficient Memory Architecture for High Performance and Low Power Applications Under Sub-threshold RegimeLecture Notes in Networks and Systems2023, 493, pp. 225–233

Madhava Rao, K., Karthik Reddy, B., Rameshkumar Reddy, C., Charan Kumar, K., Reddy, J.Y.

Implementation of on-chip high precision oscillators with RC and LC using digital compensation technique”AIMS Electronics and Electrical Engineering, 2022, 6(2), pp. 188–197

Publications (2021-22):

Gnaneshwara Chary, et al. “Device-to-Device Data Transmission Over Sound Waves Using FSK/BPSK/QPSK.” Communication, Software and Networks: Proceedings of INDIA 2022. Singapore: Springer Nature Singapore, 2022. 95-102.

Madhava Rao, K., Reddy, J.Y., Kumar, B.N., DESIGN AND ANALYSIS OF BIO INSPIRED CANTILEVER MICRO GRIPPER NEEDLE FOR SURGICAL APPLICATIONS” ARPN Journal of Engineering and Applied Sciences, 2021, 16(22), pp. 2425–2430

Mr. K Madhava Rao, et. al.Implementation Of Power Efficient Accurate And Approximate Full Adders For Image Processing Applications”Turkish Journal of Computer and Mathematics Education (TURCOMAT)

Publications (2020-21):

1804. GnaneshwaraChary, and H. Kakarla. “Low power analog multiplexers for ECG applications.”J. Phys., Conf. Ser.. Vol. 1804. No. 1. 2021.

Madhava Rao, K ,Chandra, V.S.Kumari, A.”Hardware Implementation of Pixel Comparison and Error Detection in Image” Proceedings of the 4th International Conference on Trends in Electronics and Informatics, ICOEI 2020, 2020, pp. 696–700, 9142900

Publications (2019-20):

1. Gnaneshwara chary, Poralla Divya,The International Journal of Analytical and Experimental Model Analysis “June 2020 Volume XII, issue VI, Pg. nos:1404-1410 Design and Implementation of VLSI architecture for Error correction and Detection
2. Gnaneshwara chary, Goundla Priyanka The International Journal of Analytical and Experimental Model Analysis June 2020Vol ume XII, issue VI, Pg. nos:1388-1394 Low Quantum Cost Reversible Logic Gates and QCA Architectures.
3. Madhava Rao,P. Rajesh, P. Akash, P.Pragath & M. Sai Mahesh The International Journal of Analytical and Experimental Model Analysis April-2020 volume XII,issue IV, Pg.nos :1957-1963 FPGA Based Robotic ARM Controller
4. Madhava Rao, D. Sai Shradha, Ch. Kavya Madhuri, B. Ravi, D. SudheerInternational Journal of Research in Engineering, Science and Management April-2020 Volume 4, Issue 3, Pg.nos: 332-334 Implementation of ALU by Vedic Algorithm
5. C Ramesh Kumar Reddy, Syed Muqtar Nawaz, Sureddy Sravya, Mohammed Imran International Journal of Advance Research, Ideas and Innovations in Technology May 2020 ISSN: 2454-132X Impact factor: 6.078   Volume 6, issue 2 ASIC implementation of smart home using VLSI design
6. Yeshwanth Reddy International Journal of Current Advanced ResearchApril-2020 Volume : 9 , Issue : 4 Implementation of  I2C communication protocol with RTC and EPROM using FPFA

Publications (2018-19):

Scopus:

1. A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic-   U. G. Chary, Bala Bandhavi, Naga srujana, Tripura.
2. GESTURE BASED HOME AUTOMATION SYSTEM USING SPARTAN 3A, ASIC International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 Scopus, K. Madhava Rao.

Conferences:

1. U-Turn Collision Caution System Using FPGA-(conference paper), U.Gnaneshwara chary, Tejaswini, Vishnavi Manda, Sharath Kumar
2. Madhava Rao has presented a paper on “Performance & functionality of novel Subthreshold SRAM’s using low power techniques for SoC designs”in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 15th & 16th,,October 2018,Coimbatore,india

Publications (2017-18):

1. “Garbage Waste Monitoring System using Ultrasonic Sensors on FPGA”, C. Phanindra, M. Kalyan, . B. Sruthi, Md. Shameem, Latha Bai, C. Ramesh Kumar Reddy , ISSN: 2321-9653; IC Value: 45.98; SJ Impact Factor: 6.887 Volume 6 Issue IV, April 2018.

Publications (2016-17):

1. “FPGA Implementation of Mouse Interface”, V.Pravalika , P.Bhavya Reddy,G.John , B.Anil Kumar , K.Madhava Rao , International Conference on Trends in Electronics and Informatics ICEI 2017
2. “FPGA Implementation of Industry Automated Bottle Counter”. Shivani Arvapally, Mohammed Anwar Khan, Prem Chand Vemula, Prakash Sonnaila, U. G. Chary, International Conference on Electronics, Communication and Aerospace Technology ICECA 2017.
3. “AN EFFICIENT VLSI ARCHITECTURE FOR MATRIX BASED RNS BACKWARD CONVERTER” Bhavana Rayapudi a, B.K Raju, Gnaneshwara Chary ,Pranay Deekonda,     Prashanth Ummadisett . International Conference on Computational Modeling and Security (CMS 2016)
4. “FPGA based Traffic Light Controller”, S. Venkata Kishore, Vasavi Sreeja, Vibhuti Gupta, V.Videesha, I. B. K. Raju, K. Madhava Rao, International Conference on Trends in Electronics and Informatics ICEI 2017
5. “A Novel 7-Segment Digital Clock Implementation on FPGA”. Nikhil Kumar Vuthuri , Vijaya Mahewar , Gowtham yeddluri , Eshwar sai Movva , Vandana.ch , International Conference on Trends in Electronics and Informatics ICEI 2017.

 Certifications