S.No | Name of the Laboratory | Specialized Equipment | Equipment Details |
I-SEM |
| ||
1 | Digital System Design with FPGA LAB | Synopsys, Xilinx, Nexus 4 FPGA boards | VCS |
2 | CMOS Analog IC Design LAB | Synopsys | custom compiler |
II-SEM |
| ||
3 | VLSI Advanced Physical Design LAB | Synopsys | ICC-II |
4 | System Verilog Test Benches using UVM | Synopsys | VCS |
The objectives of this lab are,
- The lab will emphasis on learning Digital circuits.
- Implemntation of Digital circuits on FPGAs.
Students are able to perform
- Understand the fundamentals of digital circuits, including logic gates, flip-flops, and sequential circuits. Explore Boolean algebra and its application in digital circuit design. Learn about combinational logic and sequential logic design principles.
- Utilize simulation tools to model and analyze digital circuits before physical implementation. Simulate various digital circuit scenarios to reinforce theoretical concepts and troubleshoot potential issues.
Finally the circuits are implemented on targeted FPGA boards
Course Objective:
- The lab will emphasis on Designing of CMOS Analog Circuits.
- Implementation of Analog circuits in Industry oriented tools.
Students are able to perform,
- Understand the fundamentals of Complementary Metal-Oxide-Semiconductor (CMOS) technology used in analog integrated circuits. Learn the design principles of essential analog building blocks, such as amplifiers, voltage references, and current mirrors. Explore techniques for sizing and optimizing CMOS transistors to achieve desired performance characteristics in analog circuits.
- Layout Design: Gain hands-on experience in creating layout designs for CMOS analog circuits, considering factors like parasitics and matching. Study methods for analyzing and minimizing noise in CMOS analog circuits, crucial for maintaining signal integrity.
- Analyze the frequency response of analog circuits and design techniques to achieve desired bandwidth and roll-off characteristics. Design and analyze CMOS operational amplifiers, covering aspects such as gain, bandwidth, and stability.
- Utilize industry-standard simulation tools for circuit verification and performance analysis.
Course Objectives:
- Synthesized Netlist is the input for Physical Design.
- Physical Design steps will complete the final Macros placement.
Students are able to perform,
- Master advanced VLSI physical design methodologies. Complete the experiments in Floor planing, Placement and Routing.
- Gain expertise in addressing timing closure challenges through techniques like clock tree synthesis and signal integrity analysis.
- Develop proficiency in using industry-standard Electronic Design Automation (EDA) tools for layout and floor planning.
Acquire skills in power optimization strategies for complex VLSI circuits
This lab focuses exclusively on
- System verilog Language for Testbenches implemntation.
- Development of verification methodologies using SV and UVM.
Students are able to perform
- Implementing effective test benches using SystemVerilog language.
- Utilizing SystemVerilog features for creating robust and scalable verification environments.
Mastering the development of verification methodologies specifically in assertions and randomization concepts.
