B.Tech: – Electronics and Communication Engineering, Vazirsultan College Of Engineering, Ku warangal,2008
M.Tech: – VLSI System Design, JNTUH, 2011
Ph.D: – Ph.D in Electronics and communication Engineering from “Sri Satya Sai University of Technology & Medical Sciences, Sehore
Teaching Experience – 11years
JNTU Registration No – 2748-160223-151411
BVRIT ID – 738
VIDWAN ID: 159042
Ratification Status – Ratified
- Young Researcher Award – 2021 Certified By Instute Of Scholars
- Guest Lecture on “Basics of VLSI & Career Guidance ” at Ratnapuri Institute of technology
- Coordinator for zon2k13- college level FEST held in 2013
- Guest Lecture on “VLSI Design” at TRR Engineering college for women in 2007
- one day workshop Inquiry-based labaratory for teachnig students design of experiments
- projects enhanced learning for engineering programs 5th oct 2018
- faculty colloquium students counselling and mentoring on dec 14th 2018
- twodays workshop “QCARES” by Qualcomm at VEDIC july 2017
- three days workshop on III program.
- SYSTEM VERILOG FUNDAMENTALS
- SYSTEM VERILOG RANDOMIZATION AND FUNCTIONAL COVARAGE
- PROGRAMMING FOR EVERYBODY(PYTHON)
- AI FOR EVERYONE
- HDL FOR FPGA
- SYSTEM VERILOG OOP & IPC
- CMOS DIGITAL IC DESIGN
- 5 day work shop on An Emarging paradigm of lowpower Computational VLSI
- one week online faculty development program on Recent Trends in VlSI
- 3 day national level FDP on Rrsearch Topics in VLSI and industry Trends
- 3 day FDP on VLSI IC DESIGN FLOW
- 5 day work shop on recent Trends in SOC design
- VLSI System design
Lecture Notes in Networks and Systems 2023, 493, pp. 225–233k ,Vasudeva Reddy, T.,Madhava Rao, K.,Santhosh Kumar, V.,Hindumathi, V. https://link.springer.com/chapter/10.1007/978-981-19-4990-6_21
- Hardware implimentation of pixel comparison and error detection in image” in 4th international conferenceon trends in electronics and informatics (ICOEI 2020 2020) June(IEEE Conference)
- DrT. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Performance & functionality of novel Subthreshold SRAM’s using low power techniques for SoC designs”in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 15th & 16th,,October 2018,Coimbatore,india(IEEE Conference)
- Dr T. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018,Mysore,India (IEEE Conference)
- K.MADHAVARAO: International Conference on Advances in Soft Computing & Communication Technologies 2K14 August 27-28th, 2014| @ VITS Hyderabad, INDIA
- “FPGA Based Traffic Light Controller”, S. Venkata Kishore, Vasavi Sreeja, G.Gupta, V.Videsha, I.B.K. Raju, K.Madhava Rao, International Conference on Trends in Electronics and Informatics, ICEI 2017. 978-1-5090-4257-9/17
- “FPGA Implementation of Mouse Interface”, V.Pravalika, P.Bhavya Reddy, G.John, B.Anil Kumar, K.Madhava Rao, International Conference on Trends in Electronics and Informatics, ICEI 2017. 978-1-5090-4257-9/17
- “Schmitt –trigger based S-Ram design For ultra low voltage peocess”- International journal of advances in soft computing technology, volume 4 ,special issue of ICASCCT 2K14@ISSN:2229-3515.
- “Implementation of on-chip high precision oscillators with RC and LC using digital compensation technique” Madhava Rao, K.,Karthik Reddy, B.,Rameshkumar Reddy, C.,Charan Kumar, K.,Reddy, J.Y.,AIMS Electronics and Electrical Engineering, 2022, 6(2), pp. 188–197, https://www.aimspress.com/article/doi/10.3934/electreng.2022012?viewType=HTML
- “DESIGN AND ANALYSIS OF BIO INSPIRED CANTILEVER MICRO GRIPPER NEEDLE FOR SURGICAL APPLICATIONS”Reddy, T.V.,Rao, K.M.,Reddy, J.Y.,Kumar, B.N., Reddy R.A. ARPN Journal of Engineering and Applied Sciencesthis link is disabled, 2021, 16(22), pp. 2425–2430. http://www.arpnjournals.org/jeas/research_papers/rp_2021/jeas_1121_8759.pdf
- “FPGA based Robotic ARM Controller” in The international Journalof Analytical and Experimental Modal analysis Volume XII issue IV APRIL-2020.(UGC Recognized)
- “Implementation of ALU by VedicAlgorithm” International Journal of Research in Engineering, Science and Management Volume-3, Issue-4, April-2020 www.ijresm.com | ISSN (Online) (UGC Recognized)
- Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power applications” in international journal of Recent Technology and Engineering ISSN: 2277-3878 (Online), Volume-8 Issue-5, January 2020. Page No. 3361-3366. (SCOPUS)
- “MEMS Design Techniques and Performance Estimation in Connected Cars” International Journal of Innovative Technology and Exploring Engineering (IJITEE)ISSN: 2278-3075, Volume-9 Issue-2, December 2019 (SCOPUS)
- Dr. T.Vasudeva Reddy &k.MadhavaRao has presented a paper on “Novel strategies ofLow power Subthreshold SRAM designs under 32nm for real-time applications.” in InternationalConference on Computational and Intelligent Techniques for Automation of Engineering Systems (CITAES), Scopus Nov 30Th&1st December
- K. Madhava Rao, GESTURE BASED HOME AUTOMATION SYSTEM USING SPARTAN 3A, ASIC International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 Scopus UGC RECOGNIZED JOURNALS
- K. Madhava Rao, et al published paper on “Design & comparison of novel low power, sub threshold Schmitt trigger based SRAM & source coupled logic for cognitive applications. In Open Access International Journal Of Science & Engineering, Volume 2, Issue , November 2017||ISSN (Online) 2456-3293.
- K. Madhava Rao, et al published paper on “Design & Analysis of Single Bit Sub-Threshold SRAM using Traditional SRAM Design under 32nm Design” Volume 5, Issue XI, November 2017,in International Journal for Research in Applied Science & Engineering Technology.
- K. Madhava Rao, et al published paper on “Design, Simulation & Comparison Of Novel Tg8t SRAM With Traditional SRAM Design In Open Access International Journal Of Science & Engineering, Volume 2,Issuexii,December 2018||ISSN (Online) 2456-3293.(UGC approved)
- CH. Sagar, K.MADHAVARAO, D. Naga Poornima “Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA”, INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 3 /AUG 2015
- “Parallel Self Timed Adder using Full Swing GDI” International journal of Research advancement in computer science and communications.
- “Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA” International Journal Of Professional Engineering Studies Volume V /Issue 3 /AUG 2015
- “An FPGA based high speed double precision Floating point multiplier using Verilog” International Journal Of Research in Advanced Engineering technologies Volume 4, Issue 5 AUG 2015.
- A MAGNETO SENSITIVE ASSEMBLY FOR INTERACTIVE ELECTRONIC DEVICES”
- OPTIMIZED ULTRA-LARGE SCALE SOC TEST CONTROL ARCHITECTURE WITH SCAN TEST FOR BANDWIDTH MANAGEMENT
- Scan Test Bandwidth Management For Ultra-large-Scale System-On-Chip Architectures
