Faculty Coordinator: Mr. U.Gnaneshwara Chary
Faculty Members: Dr. K. Madhava Rao, Mr. K. Ananda Kumar, Mr. C. Ramesh Kumar Reddy, Mrs. Vandana. Ch, Mr. K. Charan Kumar, Dr. B. Pavan Kumar, Mrs. Swagatha Devi,
Major Hardware / EDA Tools
| S.No | Major Hardware / Software |
| 1 | SYNOPSYS TOOLS |
| 2 | XILINX ISE 14.4 |
| 3 | XUPV5-LX110T BOARD |
| 4 | SPARTAN 3A XC3SD1800 DSP STARTAN KIT |
| 5 | SPARTAN2 XC2S100 FPGA |
SERVER
| S.No | Major Hardware / Software |
| 6 | POWERED BY LINUX SERVER |
| 7 | HP PROLIAN ML 150 G5 SERVER,QUAD- CORE INTEL XEON |
| 8 | HP 19 “ TFT MONITOR |
NETWORK CONNECTION NODES
| 9 | HP DX 2480 DESKTOPS |
| 10 | INTEL PENTIUM CORE2 DUO E4600 |
| 11 | 1 GB RAM PX976,320 GB HDD, HP DVD RW |
| 12 | 969 SATA KEY BOARD /MOUSE, 19”TFT MONITORS |
DATA SWITCH
| 13 | 10/100 FAST ETHERNET SWITCH 24 PORTS |
| 14 | D-LINK DES-1024D |
ELECTRICAL EQUIPMENT
| 15 | 10 KVA UPS HALF AN HOUR BACKUP |
. This Lab exposes the students to latest in IC Design Technology. The main objective of the center is to enabling the excellence in training for VLSI Technology and to bridge the gap between academic and VLSI industry.
5-Day Workshop on “Advanced Digital Design using Verilog HDL”
Department of ECE, B V Raju Institute of Technology, Narsapur has conducted 5-Day Workshop on “Advanced Digital Design using Verilog HDL” in association with LUCID VLSI Technologies, Hyderabad from 17th to 20th and 22nd December 2018.
Venue:
| CVD Lab, Dept of ECE, BVRITN |
OBJECTIVE OF THE WORKSHOP:
| To Enhance Student Skills in designing Digital Circuits and modeling them by using Verilog HDL. |
PARTICIPANTS
| Total 44 Students from II B.Tech ECE (40) and III B.Tech ECE (4) have participated in this workshop. |
RESOURCE PERSONS:
| Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad. |
FACULTY ATTENDED:
| Mr. I.B.K Raju, Assoc. Prof, ECE |
| Mr.U.Gnaneshwara Chary, Asst. Prof, ECE |
| Mr.K.Madhava Rao, Asst. Prof, ECE |
| Mr.K.Ananda Kumar, Asst. Prof, ECE |
| Mr.C.Ramesh Kumar Reddy, Asst. Prof, ECE |
| Mr.J.Yeshwanth Reddy, Asst. Prof, ECE |
| Mrs S.Venkata Laxmi, Lab Assistant, ECE |
DAY WISE SESSIONS CONDUCTED:
| Day | Topic |
| Day 1 | Digital Fundamentals And Structural Coding in Verilog |
| Day 2 | Large Sized Combinational Circuit Design |
| Day 3 | Coding Sequential Elements |
| Day 4 | Industry Challenges & Solutions |
| Day 5 | Mini Project and Certification Exam |
WORKSHOP OUTCOME:
| Students were able to do RTL modeling of digital circuits. |
| Students gained practical experience by designing, modeling, implementing and verifying several Digital Circuits. |
| Students were able to do micro project on digital design. |
Faculty Publications 2018-19
INTERNATIONAL/NATIONAL JOURNALS (SCOPUS)
|
IEEE CONFERENCES
|
5-Day WORKSHOP on “VLSI Design Flow using SYNOPSYS Tools”: |
| CVD conducted 5-Day workshop on “VLSI Design Flow using SYNOPSYS Tools” in collaboration with SYNOPSYS, Hyd and EIGEN Technologies, New Delhi during 29th December 2015 -2nd January 2016 at BVRIT, Narsapur. Around 8 Engineers from Synopsys and 2 Engineers from EIGEN Technologies have delivered expert lectures. . |
3-Day WORKSHOP on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC”: |
| Conducted 3-Day workshop on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC” in collaboration with XILINX,Hyd, Coreel Technologyes, Hyd & IEEE, Hyd during 9th-11th March 2015. Bhaarathe Malliah Gowder, Discipline Chief, Cyient Ltd., Hyderabad is invited as a chief guest for inaugural ceremony. Around 4 Engineers from Coreel Technologyes have delivered expert lectures. |
INTRENSHIPS |
| CYIENT, Hyd have offered 6 Months Internship to V.Srikanth (12211AE9), Shyam Sundet Reddy (12211AD4), Sangameshwar (12211AC6), Siddartha Reddy (12211AD6) B.Tech Student |
| Research Center Imarat (RCI) ,Hyderabad have offered 1 year Internship to B.Malathi(14211D5706) , P.Shyamala(14211D5713), M.Tech students |
| Smarttrak, Hyderabad have offered 1 year internship to Sheri Mounika(14211D5710), M.Tech Student |
| Tevatyron Technology, Noida have offered 1 year internship to T.Vishwabindu (14211D5720),M.Tech Student |
| Manjeera Digital Systems have offered 1 Year internship to R.Manikanta (14211D5707), Sushanth Reddy (14211D5717), M.Tech Students. |
| Synopsys have offered 1year Pay internship to Kavya Paruchuri(13211D5704), G.Abhishek(13211D5708),K.Akhila(13211D5709), M.Harish Kumar(13211D5715), Sai Kriranmayee(13211D5719), M.Tech Students and Rajesh Kotha(11211A04A3), B.Tech student during 2015-16. |
BVRIT – Cyient Incubation Centre
Objective of this center is to create academic center of excellence in semiconductor technology. The key activities of the above center is to provide domain training by VLSI experts from CYIENT to students supported by two faculty members Mr.I.B.K Raju and U. Gnaneshwara chary from Dept of Electronics and communication, BVRIT who also got trained by CYIENT. Training is followed by Identify the real time problems and finding the technological solutions and validating the idea (proof of concept). Once the idea is formulated and validated design and implementation will be proceeded.
Major Hardware / Software
| S.No | Major Hardware / Software |
| 1 | HP Computers |
| 2 | VERTEX 5 |
| 3 | SPARTON 3E, 3A |
| 4 | SYNOPSYS EDA Tools for ASIC Solutions |
| 5 | XILINX ISE |
OUTCOMES ACHIEVED:
With the Establishment of BVRIT-CYIENT Incubation Center we achieved new heights by training the students at Industrial level of VLSI Knowledge set. Center played an important role in placement & internships of B.Tech students. The following students are benefited in Placement and Internships.
| S.No | Student Name | Company Placed in |
| 1 | MANASA SAROVARI | GGK Technologies / Soctronics |
| 2 | ANJALI | TECHMAHINDRA |
| 3 | ASHWINI | TECHMAHINDRA |
| 4 | ANWAR KHAN | TECHMAHINDRA |
| 5 | VASAVI SREEJA | TECHMAHINDRA |
| 6 | VIBHUTI | TECHMAHINDRA |
| 7 | VIDEESHA | TECHMAHINDRA |
| 8 | BHAVYA REDDY | CAPGEMINI |
| 9 | GAYATHRI | CAPGEMINI |
| 10 | PRAVALIKA | CAPGEMINI |
| 11 | SHIVANI | CAPGEMINI |
| 12 | VENKATA KISHORE | CAPGEMINI / ADEPT CHIPS |
| 13 | JOHN | CAPGEMINI |
| 14 | PREM CHAND | ADEPT CHIPS |
| 14 | BHUVANESHWARI | NTT DATA |
BATCH-II
TRAINING PHASE
| Details of the Training | Details of Resource Persons | Date & Time Duration | No. of Students Benefited | Remarks |
| 6-Months Hands on Training Program on VLSI Design | CYIENT Industrial Experts: Avinash Yedlapati, Project Manager Mandeep Singh, Project Lead Vineeth Tandon, Assistant Project Manager Prasad Raju, Assistant Project Manager Lingaiah Bontha, Team Lead Vinay, Associate Engineer BVRITN Academic Experts: I.B.K.Raju, Assoc Prof, ECE Department U.Gnaneshwara Chary, Asst Prof, ECE Department | 18/07/16 to 31/12/16 | 24 UG Students | Completed Successfully |
PROJECT PHASE
| Details of the Activity | Title of Project | Date & Time Duration | No. of Students Benefited | Remarks |
| Ideation & Brain Storming | ASIC Implementation of NAND Flash Controller | 1/3/16 to 31/3/16 | 21 (17 UG+4 PG) | Completed Successfully |
| RTL Design | ASIC Implementation of NAND Flash Controller | 4/7/2016 to 30/9/2016 | 21 (17 UG+4 PG) | Completed Successfully |
| RTL Verification | ASIC Implementation of NAND Flash Controller | 1/10/2016 | 21 (17 UG+4 PG) | Completed Successfully |
TRAINING PHASE
Faculty Training
| Training Details: 4-Month Faculty Training Program |
| Dates: 2/11/15 to 29/2/16 |
| Venue CYIENT Ltd ,Hyd |
| No. of Students Benefited: 2 (I.B.K.Raju, Assoc Prof & U.Gnaneshwara Chary, Asst Prof ) |
| Status of Training sessions: Completed Successfully |
Student Training
| Training Details: 3-Months Hands on Training Program on VLSI Design |
| Dates: 2/12/15 to 29/2/16 |
| No. of Students Benefited: 21 (17 UG+4 PG) |
| Status of Training sessions: Completed Successfully |
Training Details
| Date | Topics covered | Resource Persons |
| 02/12/2015 | ASIC/FPGA Design Flow | Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD |
| 03/12/2015 to 05/12/2015 | Exercises on Digital and Advanced Digital Designs | I.B.K. Raju &Gnaneshwara chary |
| 07/12/2015 | FSM Design | Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD |
| 09/12/2015 to 12/12/2015 | Exercises/Labs on Verilog/State Machines/System Verilog | I.B.K. Raju &Gnaneshwara chary |
| 14/12/2015 | Verification | Mr. Vineet, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD |
| 16/12/2015 to 19/12/2015 | Exercises/Labs on writing effective Testbenches | I.B.K. Raju &Gnaneshwara chary |
| 22/12/2015 to 26/12/2015 | Exercises/Labs on RTL Code and Testbenches with Code Coverage options | I.B.K. Raju & Gnaneshwara chary |
| 28/12/2015 | Synthesis | Mr. P. Madhan Mohan,Team Lead, CYIENT, Mr. B.Lingaiah, Team Lead, CYIENT |
| 29/12/2015 to 05/01/2016 | Exercises/Labs on Synthesis of Digital Circuits | I.B.K. Raju & Gnaneshwara chary |
| 07/01/2016 | System Verilog verification Methodology | Mr. Vineet, Manager, CYIENT, HYD |
| 20/01/2016 | Logic Equivalence Checking & Static Timing Analysis | Mr. P. Madhan,Team Lead, CYIENT, Mr. P. Bhargava, Team Lead, CYIENT |
| 21/01/2016 to 23/01/2016 | Exercises/Labs on LEC | I.B.K. Raju & Gnaneshwara chary |
| 28/1/2016 | Physical Design | Mr. K.Madhusudan Rao, Project Manager,CYIENT, HYD, Mr. Konda Reddy, Tech lead, CYIENT, HYD |
| 04/02/2016 | Analog Layout Design | Mr. Raja Randham, Layout Manager, CYIENT, HYD, Mr. Vishnu, Layout Engineer, CYIENT, HYD |
