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Center for VLSI Design

Faculty Coordinator:Mr.I.B.K.Raju

Faculty Members:Mr. U.Gnaneswara Chary, Mr.Ananada Kumar, Mrs.Vandana, Mr.Madhava Rao, Mr.Ramesh Kumar Reddy, Mr.Yeshwarnth

Major Hardware / EDA Tools

S.No Major Hardware / Software
1 SYNOPSYS TOOLS
2 XILINX ISE 14.4
3 XUPV5-LX110T BOARD
4 SPARTAN 3A XC3SD1800 DSP STARTAN KIT
5 SPARTAN2 XC2S100 FPGA

SERVER

S.No Major Hardware / Software
6 POWERED BY LINUX SERVER
7 HP PROLIAN ML 150 G5 SERVER,QUAD- CORE INTEL XEON
8 HP 19 “ TFT MONITOR

NETWORK CONNECTION NODES

9 HP DX 2480 DESKTOPS
10 INTEL PENTIUM CORE2 DUO E4600
11 1 GB RAM PX976,320 GB HDD, HP DVD RW
12 969 SATA KEY BOARD /MOUSE, 19”TFT MONITORS

DATA SWITCH

13 10/100 FAST ETHERNET SWITCH 24 PORTS
14 D-LINK DES-1024D

ELECTRICAL EQUIPMENT

15 10 KVA UPS HALF AN HOUR BACKUP

This Lab exposes the students to latest in IC Design Technology. The main objective of the center is to enabling the excellence in training for VLSI Technology and to bridge the gap between academic and VLSI industry.

Training Offered:

Level 1

Semester Module & Contents
II Year 2nd Sem Training on Advance Digital Design, Training on HDL, Training on CMOS
III Year 1st Sem Training on VCS@Synopsys, Training on Custom Designer @Synopsys

Corporate Training:

Hosted Adeptchips Corporate Training from feb 2018 to May, 2018.

Contests/Events Participated:

Synopsys Design Contest-2017:

Project Name of the students Mentor
Resistor calibration Circuit for Transmission Lines using Custom Designer @Synopsys Naga Srujana, Bala Bandhavi Mr. U.Gnaneshwara chary

Certification Courses:

Synopsys Design Contest-2017:

Nmae of the Course Name of the students and faculty benefited Duration
“Advanced Digital Design Using Verilog” by LUCID Technologies. 48 students + 6 Faculty 4-Days

Projects 2017-18:

Application:Memory Techniques, Mobile Robot, Low Power applications, Analog design

Project Code Name of the Students Name of the Project Name of the Mentor
VL0001 M.Bala Bandhavi, M.Thripura Reddy, D.Naga Srujana, M.Vaishnavi CMOS Resistance Calibration circuit for PCB Transmission Lines Mr. U.G.Chary
VL0002 P.H.H.Naga Vamsi, N.Prudhvi Raj, Seema Sulthana, R.Chandana FPGA Implementation of I2C Communication Protocol Mr.I.B.K.Raju
VL0003 M.D Shameem, K Latha Bai, M Kalyan Kumar, C.Phanindra Garbage Waste Monitoring System using Ultrasonic sensors on FPGA Mr. Ramesh Kumar Reddy
VL0004 B.V.N.Sai Keerthi, M.Swarnamala, B.Srujan kumar Goud, P.Chandrika, Y.Ravi kiran Implementation of SRAM design using different Techniques Mr. J. Yeshwanth Reddy
VL0005 Hari Teja, P.Shruthi, Preethi.K, Roopa Gesture Control Robot Using FPGA Mr. Madhava Rao
VL0006 T.Tejashwini, Sarath Chandra Reddy, D.Bhavya, M.Vaishnavi Parallel self timed adder using Full Swing GDI technology Mr.U.G.Chary

Publications:

Synopsys Design Contest-2017:

Mr.C.Ramesh Kumar Reddy, Mr.C.Phanindra, Mr.M.Kalyan, Ms.C.B.Sruthi, Mr.Md.Shameem, Ms.Latha Bai, “Garbage Waste Monitoring System using Ultrasonic Sensors on FPGA” published in International Journal for Research in Applied Science and Engineering Technology (IJRASET), International peer reviewed, online journal Thomosn Reuters Researcher ID: N-9681- 2016, Crossref DOI Number: 10.22214, Volume-6, Issue-4, April-2018.
Mr. U.Gnaneshwara Chary, Ms.M.Bala Bandhavi, Ms.M.Thripura Reddy, Ms.D. Naga Srujana,“A Low Power Analysis of Calibration Resistance Circuit using DTMOS Logic” presented in National Conference on “Recent Advances in Power, Industrial Drives and Energy Evolutionary Technologies(RAPIDEET-2018)” during 20th &21st April-2018.
Mr. K.Madhava Rao, Mr.B.Hari Teja, Ms.P.Sruthi, Ms.N.Roopa, Ms.K.Preeti, “Gesture Based Home Automation System Using SPARTAN 3A, ASIC” presented in National Conference on “Recent Advances in Power, Industrial Drives and Energy Evolutionary Technologies (RAPIDEET-2018)” during 20th &21st April-2018.

5-Day WORKSHOP on “VLSI Design Flow using SYNOPSYS Tools”:
CVD conducted 5-Day workshop on “VLSI Design Flow using SYNOPSYS Tools” in collaboration with SYNOPSYS, Hyd and EIGEN Technologies, New Delhi during 29th December 2015 -2nd January 2016 at BVRIT, Narsapur. Around 8 Engineers from Synopsys and 2 Engineers from EIGEN Technologies have delivered expert lectures. .
3-Day WORKSHOP on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC”:
Conducted 3-Day workshop on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC” in collaboration with XILINX,Hyd, Coreel Technologyes, Hyd & IEEE, Hyd during 9th-11th March 2015. Bhaarathe Malliah Gowder, Discipline Chief, Cyient Ltd., Hyderabad is invited as a chief guest for inaugural ceremony. Around 4 Engineers from Coreel Technologyes have delivered expert lectures.

INTRENSHIPS
CYIENT, Hyd have offered 6 Months Internship to V.Srikanth (12211AE9), Shyam Sundet Reddy (12211AD4), Sangameshwar (12211AC6), Siddartha Reddy (12211AD6) B.Tech Student
Research Center Imarat (RCI) ,Hyderabad have offered 1 year Internship to B.Malathi(14211D5706) , P.Shyamala(14211D5713), M.Tech students
Smarttrak, Hyderabad have offered 1 year internship to Sheri Mounika(14211D5710), M.Tech Student
Tevatyron Technology, Noida have offered 1 year internship to T.Vishwabindu (14211D5720),M.Tech Student
Manjeera Digital Systems have offered 1 Year internship to R.Manikanta (14211D5707), Sushanth Reddy (14211D5717), M.Tech Students.
Synopsys have offered 1year Pay internship to Kavya Paruchuri(13211D5704), G.Abhishek(13211D5708),K.Akhila(13211D5709), M.Harish Kumar(13211D5715), Sai Kriranmayee(13211D5719), M.Tech Students and Rajesh Kotha(11211A04A3), B.Tech student during 2015-16.