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Center for VLSI Design

Faculty Coordinator: Mr. U.Gnaneshwara Chary 

Faculty Members: Dr. K. Madhava Rao, Mr. K. Ananda Kumar, Mr. C. Ramesh Kumar Reddy, Mrs. Vandana. Ch, Mr. K. Charan Kumar, Dr. B. Pavan Kumar, Mrs. Swagatha Devi, 

Major Hardware / EDA Tools 

S.NoMajor Hardware / Software
1SYNOPSYS TOOLS
2XILINX ISE 14.4
3XUPV5-LX110T BOARD
4SPARTAN 3A XC3SD1800 DSP STARTAN KIT
5SPARTAN2 XC2S100 FPGA

 

SERVER 

S.NoMajor Hardware / Software
6POWERED BY LINUX SERVER
7HP PROLIAN ML 150 G5 SERVER,QUAD- CORE INTEL XEON
8HP 19 “ TFT MONITOR

 

NETWORK CONNECTION NODES 

9HP DX 2480 DESKTOPS
10INTEL PENTIUM CORE2 DUO E4600
111 GB RAM PX976,320 GB HDD, HP DVD RW
12969 SATA KEY BOARD /MOUSE, 19”TFT MONITORS

 

DATA SWITCH 

1310/100 FAST ETHERNET SWITCH 24 PORTS
14D-LINK DES-1024D

 

ELECTRICAL EQUIPMENT 

1510 KVA UPS HALF AN HOUR BACKUP

. This Lab exposes the students to latest in IC Design Technology. The main objective of the center is to enabling the excellence in training for VLSI Technology and to bridge the gap between academic and VLSI industry.

 

5-Day Workshop on “Advanced Digital Design using Verilog HDL”

Department of ECE, B V Raju Institute of Technology, Narsapur has conducted 5-Day Workshop on “Advanced Digital Design using Verilog HDL” in association with LUCID VLSI Technologies, Hyderabad from 17th to 20th and 22nd December 2018.

 

Venue: 

CVD Lab, Dept of ECE, BVRITN

 

OBJECTIVE OF THE WORKSHOP: 

To Enhance Student Skills in designing Digital Circuits and modeling them by using Verilog HDL.

 

PARTICIPANTS 

Total 44 Students from II B.Tech ECE (40) and III B.Tech ECE (4) have participated in this workshop.

 

RESOURCE PERSONS: 

Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad.

 

FACULTY ATTENDED: 

Mr. I.B.K Raju, Assoc. Prof, ECE
Mr.U.Gnaneshwara Chary, Asst. Prof, ECE
Mr.K.Madhava Rao, Asst. Prof, ECE
Mr.K.Ananda Kumar, Asst. Prof, ECE
Mr.C.Ramesh Kumar Reddy, Asst. Prof, ECE
Mr.J.Yeshwanth Reddy, Asst. Prof, ECE
Mrs S.Venkata Laxmi, Lab Assistant, ECE

 

DAY WISE SESSIONS CONDUCTED: 

DayTopic
Day 1Digital Fundamentals And Structural Coding in Verilog
Day 2Large Sized Combinational Circuit Design
Day 3Coding Sequential Elements
Day 4Industry Challenges & Solutions
Day 5Mini Project and Certification Exam

 

WORKSHOP OUTCOME: 

Students were able to do RTL modeling of digital circuits.
Students gained practical experience by designing, modeling, implementing and verifying several Digital Circuits.
Students were able to do micro project on digital design.

 

Faculty Publications 2018-19 

INTERNATIONAL/NATIONAL JOURNALS (SCOPUS)

  1. Dr. T.Vasudeva Reddy &k.MadhavaRao has presented a paper on “Novel strategies ofLow power Subthreshold SRAM designs under 32nm for real-time applications.” in InternationalConference on Computational and Intelligent Techniques for Automation of Engineering Systems (CITAES), Scopus Nov 30Th&1st December
  2. K. Madhava Rao, GESTURE BASED HOME AUTOMATION SYSTEM USING SPARTAN 3A, ASIC International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 Scopus UGC RECOGNIZED JOURNALS
  3. K. Madhava Rao, et al published paper on “Design & comparison of novel low power, sub threshold Schmitt trigger based SRAM & source coupled logic for cognitive applications. In Open Access International Journal Of Science & Engineering, Volume 2, Issue , November 2017||ISSN (Online) 2456-3293.
  4. K. Madhava Rao, et al published paper on “Design & Analysis of Single Bit Sub-Threshold SRAM using Traditional SRAM Design under 32nm Design” Volume 5, Issue XI, November 2017,in International Journal for Research in Applied Science & Engineering Technology.
  5. K. Madhava Rao, et al published paper on “Design, Simulation & Comparison Of Novel Tg8t SRAM With Traditional SRAM Design In Open Access International Journal Of Science & Engineering, Volume 2,Issuexii,December 2018||ISSN (Online) 2456-3293.(UGC approved)
  6. Udari Gnaneshwara chary, J. Yeshwanth Reddy published a paper on Analysis of Clockfeedthrough and Chargeinjection using cadence 180nm Technology in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)
  7. Udari Gnaneshwara chary published a paper on A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)

IEEE CONFERENCES

  1. DrT. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Performance & functionality of novel Subthreshold SRAM’s using low power techniques for SoC designs”in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 15th & 16th,,October 2018,Coimbatore,india
  2. Dr T. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018,Mysore,India

 

5-Day WORKSHOP on “VLSI Design Flow using SYNOPSYS Tools”:

CVD conducted 5-Day workshop on “VLSI Design Flow using SYNOPSYS Tools” in collaboration with SYNOPSYS, Hyd and EIGEN Technologies, New Delhi during 29th December 2015 -2nd January 2016 at BVRIT, Narsapur. Around 8 Engineers from Synopsys and 2 Engineers from EIGEN Technologies have delivered expert lectures. .

 

3-Day WORKSHOP on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC”:

Conducted 3-Day workshop on “VLSI & Embedded Design Flow using XILINX ZYNQ SOC” in collaboration with XILINX,Hyd, Coreel Technologyes, Hyd & IEEE, Hyd during 9th-11th March 2015. Bhaarathe Malliah Gowder, Discipline Chief, Cyient Ltd., Hyderabad is invited as a chief guest for inaugural ceremony. Around 4 Engineers from Coreel Technologyes have delivered expert lectures.

 

INTRENSHIPS

CYIENT, Hyd have offered 6 Months Internship to V.Srikanth (12211AE9), Shyam Sundet Reddy (12211AD4), Sangameshwar (12211AC6), Siddartha Reddy (12211AD6) B.Tech Student
Research Center Imarat (RCI) ,Hyderabad have offered 1 year Internship to B.Malathi(14211D5706) , P.Shyamala(14211D5713), M.Tech students
Smarttrak, Hyderabad have offered 1 year internship to Sheri Mounika(14211D5710), M.Tech Student
Tevatyron Technology, Noida have offered 1 year internship to T.Vishwabindu (14211D5720),M.Tech Student
Manjeera Digital Systems have offered 1 Year internship to R.Manikanta (14211D5707), Sushanth Reddy (14211D5717), M.Tech Students.
Synopsys have offered 1year Pay internship to Kavya Paruchuri(13211D5704), G.Abhishek(13211D5708),K.Akhila(13211D5709), M.Harish Kumar(13211D5715), Sai Kriranmayee(13211D5719), M.Tech Students and Rajesh Kotha(11211A04A3), B.Tech student during 2015-16.

 

BVRIT – Cyient Incubation Centre

Objective of this center is to create academic center of excellence in semiconductor technology. The key activities of the above center is to provide domain training by VLSI experts from CYIENT to students supported by two faculty members Mr.I.B.K Raju and U. Gnaneshwara chary from Dept of Electronics and communication, BVRIT who also got trained by CYIENT. Training is followed by Identify the real time problems and finding the technological solutions and validating the idea (proof of concept). Once the idea is formulated and validated design and implementation will be proceeded.

 

Major Hardware / Software 

S.NoMajor Hardware / Software
1HP Computers
2VERTEX 5
3SPARTON 3E, 3A
4SYNOPSYS EDA Tools for ASIC Solutions
5XILINX ISE

 

OUTCOMES ACHIEVED:

With the Establishment of BVRIT-CYIENT Incubation Center we achieved new heights by training the students at Industrial level of VLSI Knowledge set. Center played an important role in placement & internships of B.Tech students. The following students are benefited in Placement and Internships. 

S.NoStudent NameCompany Placed in
1MANASA SAROVARIGGK Technologies / Soctronics
2ANJALITECHMAHINDRA
3ASHWINITECHMAHINDRA
4ANWAR KHANTECHMAHINDRA
5VASAVI SREEJATECHMAHINDRA
6VIBHUTITECHMAHINDRA
7VIDEESHATECHMAHINDRA
8BHAVYA REDDYCAPGEMINI
9GAYATHRICAPGEMINI
10PRAVALIKACAPGEMINI
11SHIVANICAPGEMINI
12VENKATA KISHORECAPGEMINI / ADEPT CHIPS
13JOHNCAPGEMINI
14PREM CHANDADEPT CHIPS
14BHUVANESHWARINTT DATA

 

BATCH-II

TRAINING PHASE 

Details of the TrainingDetails of Resource PersonsDate & Time DurationNo. of Students BenefitedRemarks
6-Months Hands on Training Program on VLSI Design

CYIENT Industrial Experts:

Avinash Yedlapati, Project Manager

Mandeep Singh, Project Lead

Vineeth Tandon, Assistant Project Manager

Prasad Raju, Assistant Project Manager

Lingaiah Bontha, Team Lead

Vinay, Associate Engineer

BVRITN Academic Experts:

I.B.K.Raju, Assoc Prof, ECE Department

U.Gnaneshwara Chary, Asst Prof, ECE Department

18/07/16 to 31/12/1624 UG StudentsCompleted Successfully

 

PROJECT PHASE 

Details of the ActivityTitle of ProjectDate & Time DurationNo. of Students BenefitedRemarks
Ideation & Brain StormingASIC Implementation of NAND Flash Controller1/3/16 to 31/3/1621 (17 UG+4 PG)Completed Successfully
RTL DesignASIC Implementation of NAND Flash Controller4/7/2016 to 30/9/201621 (17 UG+4 PG)Completed Successfully
RTL VerificationASIC Implementation of NAND Flash Controller1/10/201621 (17 UG+4 PG)Completed Successfully

 

TRAINING PHASE

Faculty Training

Training Details: 4-Month Faculty Training Program
Dates: 2/11/15 to 29/2/16
Venue CYIENT Ltd ,Hyd
No. of Students Benefited: 2 (I.B.K.Raju, Assoc Prof & U.Gnaneshwara Chary, Asst Prof )
Status of Training sessions: Completed Successfully

 

Student Training

Training Details: 3-Months Hands on Training Program on VLSI Design
Dates: 2/12/15 to 29/2/16
No. of Students Benefited: 21 (17 UG+4 PG)
Status of Training sessions: Completed Successfully

 

Training Details

DateTopics coveredResource Persons
02/12/2015ASIC/FPGA Design FlowMr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
03/12/2015 to 05/12/2015Exercises on Digital and Advanced Digital DesignsI.B.K. Raju &Gnaneshwara chary
07/12/2015FSM DesignMr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
09/12/2015 to 12/12/2015Exercises/Labs on Verilog/State Machines/System VerilogI.B.K. Raju &Gnaneshwara chary
14/12/2015VerificationMr. Vineet, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
16/12/2015 to 19/12/2015Exercises/Labs on writing effective TestbenchesI.B.K. Raju &Gnaneshwara chary
22/12/2015 to 26/12/2015Exercises/Labs on RTL Code and Testbenches with Code Coverage optionsI.B.K. Raju & Gnaneshwara chary
28/12/2015SynthesisMr. P. Madhan Mohan,Team Lead, CYIENT, Mr. B.Lingaiah, Team Lead, CYIENT
29/12/2015 to 05/01/2016Exercises/Labs on Synthesis of Digital CircuitsI.B.K. Raju & Gnaneshwara chary
07/01/2016System Verilog verification MethodologyMr. Vineet, Manager, CYIENT, HYD
20/01/2016Logic Equivalence Checking & Static Timing AnalysisMr. P. Madhan,Team Lead, CYIENT, Mr. P. Bhargava, Team Lead, CYIENT
21/01/2016 to 23/01/2016Exercises/Labs on LECI.B.K. Raju & Gnaneshwara chary
28/1/2016Physical DesignMr. K.Madhusudan Rao, Project Manager,CYIENT, HYD, Mr. Konda Reddy, Tech lead, CYIENT, HYD
04/02/2016Analog Layout DesignMr. Raja Randham, Layout Manager, CYIENT, HYD, Mr. Vishnu, Layout Engineer, CYIENT, HYD