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EAMCET| ICET| ECET| CODE: BVRI| PGECET| CODE: BVRI1

Welcome to BVRITN

Center for VLSI Design and Applications

VLSI Automation Centre

Faculty Coordinator : Dr. M C Chinnaiah

Faculty Members : Mr.V.Kishore, Mr.Mudasar Basha, Mrs.G.Divya Vani, Mrs.K.Anusha, Ms.Asha Rani, Ms.Keerthi,Mr.RamaRao

Faculty Coordinator : Dr. M C Chinnaiah

Faculty Members : Mr.V.Kishore, Mr.Mudasar Basha, Mrs.G.Divya Vani, Mrs.K.Anusha, Mrs.Asha Rani, Ms.T. Keerthi,Mr.Ch. RamaRao

LIST OF SOFTWARES

S.No Software
1 XILINX ISE 14.7
2 VIVADO Design Suite

LIST OF HARDWARES(PROCESSORS)

S.No FPGAs & CPLD
1 ATLYS SPARTAN 6
2 NEXYS 3 SPARTAN 6
3 NEXYZ 4 SPARTAN 6
4 ZYNQ-ZED Boards
5 ANVYL with Pmod pack
6 ZYNQ-ZYBO Boards
7 ROBOT CHASIS WITH MOTOR DRIVER CIRCUITS

            VLSI A 1                                                           VLSI A 2

NETWORK CONNETIVITY NODES

1 Processor Core i3 HP 3330MT 2GB RAMs, DDR3,500GB HDD, 18.5” LED Monitors, HP Key Boards & Optical Mouse With ATX,230V Cabinets

NETWORK EQUIPMENT

1 10/100 Switches16 Ports
2 D-Link

ELECTRICAL EQUIPMENT

1 UPS 10 KVA with Half an Hour Back Up (ACCENTA)

Course Offered and Trainings:

Duration Course Module Outcomes
II-II Sem 1.C-DAC certification, 2. Training on Digital concepts and implementation Development of Basic verilog design using Digitl concepts
III-I Sem Training on Various Digital design Protocols Implementation of protocols on FPGA boards
III_II Sem 1.Training on PR flow, 2. Implementation of mini project concepts Participation in events, Submission of paper
IV_I & IV_II Sem Mini & Major Project Implemention Paper submission, Trying for core placements.

Faculty Best Paper Award:

Mr. Kishore Vennela Received "Best Paper Award" for his paper on "FPGA Implementation of Branch and remove algorithm for mobile robots in indoor environment" during ICMEET 2k17 - 09th & 10th Sept' 2017 at BVRIT- Hyderabad.

Kishore Best Paper

Faculty Workshops attended:

Funding project:

Funding Agency Title of Project Name of the Investigators Fund Sanctioned Duration of project
SERB A Companion type Assistive System for Elderly People using VLSI Based Service Robot P.I: Dr.M.C.Chinnaiah Rs.49,43,840 3 years

Student Participation/Achievements

Name of the Contest Name of the Students Title Mentor Academic Year
TELANGANA INNOVATION YATRA (TI YATRA) Dammalapati Nikitha, CH.ManojKumar, K.Bhavana, D. Yashwanth Krishna Driver assisting system to avert road accidents Ms. T.Keerthi 2019-2020
TI IIIDC 2018   Pritam, K Rakesh, L Sahithi Automatic Man Hole Detection System Mr. Kishore Vennela 2018-19
Prasanna, Yasaswi, Manoj Kumar Reddy Development of Embedded based tampering preventive mechanism for disposable medical devices Dr. M C Chinnaiah & K.Anusha 2018-19
K Bhavana, J Sushmitha, M Bhavitha, M Sowjanya Sri Wrist Band for women security(Women safety in the Society) Mr. Kishore Vennela 2018-19

 

vlsia4

Workshops Conducted

S.No Title of workshop Details of Resource Persons ( In-house/Industry) Date and Duration Academic Year No. of Students Benefited
1 “Research Migrations in VLSI Technology” (Digital Signal and Image Processing using Xilinx FPGA’s & Research trends in MEMS) Dr. K.Srinivasa Rao K.L.University & Mr. Nagendra –CoreEL 3 Days (11th to 13th February 2020) 2019-2020 35
2 System Design on ZYNQ using SDSoC Mr. Nagendra Bandi – Application Engineer CoreEL Technologies-India 2 Days (3rd – 4th Jan, 2019 2018-2019 35
3 A 15-Day Short Term Certified Course (STCC) on “Digital VLSI System Design” Mr. ABRAR, CDAC, Hyderabad 06-12-2018 to 19-12-2018 2018-2019 35
3 Partial Reconfiguration flow using XILINX Tools Mr. Balachander – Core EL 5 Days (19th -23rd Sep 2017) 2017-2018 31

Online Workshop Conducted During Lockdown period

S.No Title of workshop Details of Resource Persons ( In-house/Industry) Date and Duration Academic Year No. of Students Benefited
1 AN EMERGING PARADIGM OF LOW POWER COMPUTATIONAL VLSI DESIGN Mr. Madan Gopal Mekala - Star VLSI, Banglore, Dr. Syed Ershad Ahmed -BITS Pilani Hyderabad Campus, Dr. B. Srinivasu - IIT Mandi, Mr. Ravi Shankar - Xilinx, Hyderabad, Mr. Avinash Yadlapati - Mirafra Technologies, Hyderabad 5 Days (16th June 2020- 20th June 2020) 2019-2020 600

Faculty Workshops attended

Name of the faculty Title of workshop Date and Duration Details of Organizing institute
Dr. M.C.Chinnaiah, Dr. ApurvaKumari Singh, V.Kishore, MudasarBasha, G.Divyavani, CH.RamaraoP.Asharani, T.Keerthi System Design On ZYNQ using SDSOC 3rd and 4th Jan 2019 BVRIT Narsapur
P.Asharani Trends in SOC Design and Its Applications 14 to 19th Dec 2019 Vasavi College of Engineering
Dr. M.C.Chinnaiah, Dr. ApurvaKumari Singh, V.Kishore, MudasarBasha, G.Divyavani, CH.RamaraoP.Asharani, T.Keerthi Research Migrations in VLSI Technology 11 th to 13 th February 2020 BVRIT Narsapur
Dr. M.C.Chinnaiah, Dr. ApurvaKumari Singh, V.Kishore, MudasarBasha, G.Divyavani, CH.RamaraoP.Asharani, T.Keerthi An Emerging Paradigm Of Low Power Computational Vlsi Design 16th - 20th June 2020 BVRIT Narsapur
Ch. Ramarao, P.Asharani, T.Keerthi STTCon Digital VLSI System Design Using Verilog HDL 15 days (20th Nov-9th Dec) BVRIT Narsapur
V.Kishore, Mudasar Basha, G.Divyavani, K Anusha, P.Asharani FDP on Partial Reconfiguration flow using XILINX Tools 5 days (19th -23rd Sep 2017 BVRIT Narsapur
G.Divyavani Embedded Controller, Real Time Operating System and Wireless Sensor Network in Automation 5 days(19th -24th March 2018) IIT Madras

Industrial visits & Collaborations:

Name of the Industry/Organization Details of faculty visited Dates Brief details / outcome of visits
CoreEL Technologies Pvt.Ltd Dr.Chinnaiah.M.C 27th Nov 2017 To develop Prototypes

Summer Internships 2019-20

S.No Roll Number Name of the Student Company
1 17211a0482 Juluri Saichandu Constelli Signals Pvt. Ltd.
2 16211A0483 K.Rakesh Kumar HYSOC
3 16211A0418 B.Dhavalika DTDS

Summer Internships 2018-19

S.No Roll Number Name of the Student Company
1 15211A04A0 K.Harika HBL
2 15211A0442 CH.Sahithi HBL
3 15211A0404 Abhinav More HBL
4 16215a0416 Hosna Pravalika FERVENTZ SEMICODUCTOR
5 15211A0410 Arshiya FERVENTZ SEMICODUCTOR
6 15211A04E2 N.Sridevi FERVENTZ SEMICODUCTOR
7 15211A04G0 P.Chandana FERVENTZ SEMICODUCTOR
8 15211A04J0 R. Tejaswini HYSOC.
9 15211a0494 Kokkonda Prashanth Kumar HYSOC

Summer Internships 2017-2018

S.No Roll Number Name of the Student Company
1 15211A0405 A Sankeerth ORL INDUSTRIES
2 15211A0428 B. Pavan Sai ORL INDUSTRIES
3 15211A0483 K.Thanuja ECIL, HYDERABAD
4 15211A04A0 K. Harika ECIL, HYDERABAD
5 15211A0460 G. Akankasha ECIL, HYDERABAD
6 15211A0442 Ch. Sahithi ORL INDUSTRIES
7 15211A0437 Ch. Asrita Devi ECIL, HYDERABAD
8 15211A0404 Abhinav More ORL INDUSTRIES.
9 15211A0410 Arshiya ECIL, HYDERABAD
10 16215A0422 K.Sandhya Rani ECIL, HYDERABAD
11 15211A04B3 M.Monica Reddy ECIL, HYDERABAD
12 16215A0416 M. Hoshna Pravallika ECIL, HYDERABAD
13 15211A0494 K.Prashanth Kumar ECIL, HYDERABAD
14 15211A0472 I.Venika Sushma ECIL, HYDERABAD
15 15211A04H0 P.Rohith BHARAT DYNAMICS LIMITED, MEDAK
16 15211A0447 D. Vishnu Tejasvi ECIL, HYDERABAD
17 15211A04J0 R. Tejashwini BHARAT DYNAMICS LIMITED, MEDAK
18 15211A04G0 P.Chandana BHEL, RAMCHANDRA PURAM,HYDERABAD(R&D).
19 15211A04H1 Ch.Pratyusha BHEL, RAMCHANDRA PURAM,HYDERABAD(R&D)

Summer Internships 2016-17

S.No Roll Number Name of the Student Company
1 13211A0473 Mohan Shankar PHOTON ENERGY SYSTEMS
2 13211A04F4 M Swetha MSME
3 13211A04D0 G Sindooraa MSME
4 14215A0431 Sai Teja PHOTON ENERGY SYSTEMS
5 14215A0430 M.Naveen PHOTON ENERGY SYSTEMS
6 14215A0432 B.Yadagiri PHOTON ENERGY SYSTEMS
7 14215A0434 M Vinod Kumar Yadav PHOTON ENERGY SYSTEMS
8 14215A0428 D. Manisha Reddy PHOTON ENERGY SYSTEMS.
9 14215A0403 D. Himaja BHEL
10 14215A0407 P.Sowmya BHEL

Placements in Core Industries 2019-20

S.No Roll Number Name of the Student Company Placed
1 16211A0404 A. Murali Krishna CAPGEMINI & TCS-NINJA(NQT)
2 16211A0408 A.Chandrashekhar TCS-PEGA
3 17215A0406 V.Ashritha CAPGEMINI & HCL
4 16211A0459 G.Manoj Kumar Reddy TCS-PEGA & HCL
5 16211A0406 A.Yasaswi CAPGEMINI & HCL & WIPRO
6 16211A0458 G.Shilpa netha CAPGEMINI
7 16211A0442 D SravaniSathya WIPRO
8 16211A04b1 M.Rishi CAPGEMINI
9 16211A0439 D.Om Sridatta Sai Swaroop CAPGEMINI
10 16211A0418 B.Dhavalika DTDS
11 16211A0430 B.Rama Chandra Reddy HYUNDAI MOBIS & TCS-CODEVITA(Digital)
12 16211A0438 Devara Rachana CAPGEMINI & WIPRO
13 16211A04B3 M. Sowjanya Sree CAPGEMINI & HCL & L&T Technologies Pvt Ltd
14 16211A0483 K. Rakesh Kumar HYSOC
15 16211A04A0 K.Vamshi TCS-NINJA(NQT)
16 16211A0462 I. Krishna Sahithi HCL
17 16211A0486 K.Bhavana TCS-NINJA(NQT) & HCL
18 16211A04B0 M.Bhavitha HCL
19 16211A0471 D.Nithisha TECHM-PEGA & IBM-GTS
20 16211A0481 Pritam Karnnewar CAPGEMINI
21 16211A04A6 M.Vamsi CAPGEMINI & TCS-NINJA(NQT)
22 17215A0419 V. Naveen Kumar TCS-PEGA
23 16211A04N9 Yerpula Venkata Sreelakshmi HCL & IBM-GTS
24 16211A04K2 S.Madhuri INFOSYS-PEGA
25 16211A04N0 Vadapally Naga Lalitha Manoj CAPGEMINI
26 16211A04M6 Thatipamula Bhavani CAPGEMINI & HCL
27 16211A04L3 Richa Pandey TCS-CODEVITA(Ninja)
28 17215A0441 R. Sunil Kumar DIGILOGIC
29 16211A04N4 Vasam Ramya CAPGEMINI & HCL
30 16211A04G2 P.Vineeth Reddy IBM-GTS

Placements in Core Industries 2018-19

S.No Roll Number Name of the Student Company Placed
1 15211A0428 B. Pavan Sai CAPGEMINI
2 15211A0483 K.Thanuja CAPGEMINI
3 15211A04A0 K. Harika HBL
4 15211A04A3 L. Sreechaitanya INCESSANT-PEGA
5 15211A0410 Arshiya FERVENTZ SEMICONDUCTOR
6 15211A0447 D. Vishnu Tejasvi QSpider
7 15211A0442 Ch. Sahithi HBL
8 15211A0434 B. Mounika NCR/TCS-NINJA
9 15211A0437 Ch. Asrita Devi TCS-NINJA
10 15211A0404 Abhinav More CAPGEMINI/HBL
11 15211A0412 A Sathish Kumar Cognizant
12 15211A0448 D.Manoj Reddy TCS-NINJA& WIPRO-PEGA
13 15211A0494 K.Prashanth Kumar CAPGEMINI / HYSOC/VEDA-IIT
14 15211A0472 I.VenikaSushma TECHM-PEGA/CAPGEMINI/WIPRO
15 15211A04B3 M.Monica Reddy TCS-NINJA
16 15211A04H0 P.Rohith TCS-NINJA
17 15211A04G9 P.Karthik TCS-NINJA / Modak Analytics / WIPRO
18 15211A04H6 Ch.Rachana VEDA-IIT
19 15211A04J0 R. Tejashwini HYSOC
20 15211A04N1 V. Nagamani TCS-NINJA
21 15211A04N9 V. Samyukta LATENTVIEW
22 15211A04E2 N.Sridevi CAPGEMINI/FERVENTZ SEMICONDUCTOR
23 15211A04G0 P.Chandana CAPGEMINI/FERVENTZ SEMICONDUCTOR
24 15211A04H1 Ch.Pratyusha TCS-PEGA

Placements in Core Industries 2018-19

S.No Roll Number Name of the Student Company Placed
1 14211A0402 M K Ravali CAPGEMINI/ MODAK ANALYTICS
2 14211A0432 T. Hema Rani ALIENS GROUP
3 14211A0436 B.Sai Charan Rathod AASEYA SOLUTIONS
4 14211A0428 Javeria TCS
5 14211A0483 R.Neeraja CAPGEMINI
6 14211A0488 M.Neeraj TCS
7 15215A0426 A.Swapna INFOSYS
8 14211A04J0 Sai Charan Reddy.V TCS
9 14211A0491 P Archana PEGA
10 15215A0419 J Sandhya TCS
11 14211A04B1 D.Ruchitha AASEYA SOLUTIONS
12 14211A0497 D.Chupernechitha JSPIDER / AMAZON- VCC
13 14211A04A2 CH. Pooja AASEYA SOLUTIONS
14 14211A04E8 Sai Surekha A.J.N. MPHASIS / JSPIDER / TOPPR
15 14211A04F0 N.Hannah Priyanka CAPGEMINI
16 14211A04F5 P.Urmila AMAZON- VCC

Placements in 2016-17

S.No Roll Number Name of the Student Company Placed
1 13211A0418 L.Anusha Tech Mahindra
2 13211A0460 P.Likhith Capgemini / TCS
3 13211A0413 T Ananth Reddy UX Reactor
4 14215A0407 P.Sowmya Capgemini
5 13211A0437 B.Deepthi Reddy Capgemini
6 13211A0439 M.Divya Capgemini
7 14215A0403 D.Himaja Capgemini
8 13211A0447 N.Harika Capgemini
9 13211A04A4 M.Sai Chand Capgemini / ROBOSOFT
10 13211A0468 P.Manasa TechMahindra
11 13211A0473 S.Mohan Shankar HTC
12 14215A0416 S.Naga Sai Sharath TechMahindra
13 14215A0417 Y.Arun Kumar Capgemini
14 13211A04C0 R.S.S.Deepika Rani John Deere
15 13211A04B3 T.Samhitha Capgemini
16 13211A0459 Lakshmi Bhargavi CYIENT
17 14215A0428 D.Manisha Reddy Capgemini
18 13211A04F4 M.Swetha Capgemini
19 14215A0430 M.Naveen Appstek
20 13211A04D0 G.Sindhoora Capgemini
21 13211A04G4 T.Vasantha Capgemini
22 13211A04H3 B.Vinuthna J Spider
23 13211A04C1 Shaheen Begum Genpact
24 13601A0434 L. Surya Sita Mounika Capgemini
25 13211A04G1 Vamsi.T Capgemini

Projects & Publications

Conferences

“A New approach: An FPGA based Robot Navigation for Patrolling in Service Environment” by Chinnaaiah.M.C, Priyanka G, Divya Vani G, Asha jyoti M, Kishore Vennela in International Conference on Research Advances in Integrated Navigation Systems (RAINS - 2016), April 06-07, 2016, R. L. Jalappa Institute of Technology, Doddaballapur, Bangalore, India
A Versatile Autonomous Navigation Algorithm For Smart Indoor Environment using FPGA based robot by Dr.M.C.Chinnaiah, Dr.Sanjay,Dubey, K.Anusha in ICICICT-2017,IEEE Conference 7th july,2017. >

SCOPUS

“A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors”, by Asharani. P, M. C Chinnaiah, T. Keerthi, T. Sirisha, Sanjay Dubey in International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-5, March 2020.
“Implementation of Sensor Precision Mirror Rate”, by Anusha. K, Chinnaiah. M. C, Divya Vani. G, Kishore Vennela, Mudasar Basha in International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN: 2278-3075, Volume-9 Issue-5, March 2020.
“FPGA based navigation approach for visually impaired individuals”, by Divya Vani, B Rama Chandra Reddy, B Dhavalika, D. Rachana in International Journal for Research in Applied Science & Engineering Technology(IJRASET), Volume 8 | Issue 4, April 2020.
“An FPGA based snake robot”, by Mudasar Basha, Javeria Azain, K. Mounika, P. Akshitha in International Journal of Advance Research, Ideas and Innovations in Technology ISSN: 2454-132X, Impact factor: 4.295, (Volume 4, Issue 2).
“Command Control Robot using Internet of things on Field Programmable Gate Array”, by Mudasar Basha, Kusa Vamshi, Kollu Bhavana, Mala Bhavitha in Proceedings of the International Conference on Electronics and Sustainable Communication Systems (ICESC 2020), IEEE Xplore Part Number: CFP20V66-ART; ISBN: 978-1-7281-4108-4.
“Implementation of Sensor Precision Mirror Rate using FPGA”, by Anusha. K, Chinnaiah. M. C, Divya Vani. G, Kishore Vennela, Mudasar Basha in International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN: 2278-3075, Volume-9 Issue-5, March 2020.
“Deliberation of Robotic Services to Human kind using FPGA based Robot by Mudasar Basha, Siva Kumar, M.C.Chinnaiah, in 2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT).
“An FPGA based Classical Implementation of Branch and Remove algorithm” by Kishore Vennela, M.C.Chinnaaiah, Sanjay Dubey, Satya Savithri in ICMEET.
“Sensor Fusion based Polygon shaped Obstacle Avoidance using FPGA” by Kishore Vennela, Rishi Malladi, M Vamsi, M Sowjanyasree in Kishore Vennela, Rishi Malladi, M Vamsi , M Sowjanyasree.
“Implementation of Mobile Robot Navigation Mechanism using FPGA: An Edge Detection based Approach” by Kishore Vennela, M.C.Chinnaaiah, Sanjay Dubey and Satya Savithri in ICICC2K18.
“Image Processing Based Pre-Navigation Strategy for Service Robot in Reticulation Environment: Fulfillment using FPGA” by Kishore Vennela, M.C.Chinnaaiah, Sanjay Dubey and Satya Savithri
“An FPGA based cyclic navigation algorithm for mobile robots in the indoor environment” by Kishore Vennela, M. K. Ravali, G. Manisha, T. Hema Rani in International Journal of Advance Research, Ideas and Innovations in Technology ISSN: 2454-132X, Impact factor: 4.295 (Volume 4, Issue 2).
“Mobile Robot Navigation Mechanism for health service in reticulation environment: A composition using FPGA” by Kishore Vennela, M.C.Chinnaiah, Sanjay Dubey , and Muddasar Basha in RAPIDEET
“IOT based Advanced Black Box with Accident Detection and Location Tracing with Engine Auto Engine Turn off”, by Neha sulthana, Chinnaaiah. M.C, Nandan.K, T.Keerthi , T.Sirisha in International Journal of Engineering & Technology, 7 (3.29) (2018) 728-731
Dr.M.C.Chinnaaiah, Dr.Sanjay Dubey, Mrs.K.Anusha, Mr.P.S.Raju, Mr.B.Bharat, Ms.Divya.M, “Deliberation of Curvature Type Obstacles: A New Approach Using FPGA Based Robot” has received “Best Paper Award” and published in IEEE International Conference on Control, Power, Communication and Computing Technologies (ICCPCCT) held at Vimal Jyothi Engineering College, Kannur, Kerala on 23rd and 24th March,2018. ISBN: 978-1- 5386-0796- 1.
Dr.Sanjay Dubey, Ms.R.Neeraja, Ms.S.B.Arya, Mr.Neeraj Moota, “Implementation of Pick and Place Robot” published in International Journal of Creative Research Thoughts (IJCRT), UGC Refereed, Peer and Indexed Journal with ISSN: 2320-2882, Volume-6, Issue-2, April-2018.
Mr.Mudasar Basha, Ms.Javeria Azain, Ms.K.Mounika, Ms.P.Akshitha, “An FPGA based Snake Robot” published in International Journal of Advanced Research, Ideas and Innovations in Technology (IJARIIT), Peer Reviewed Journal with scholarly online, open access, peer-reviewed and fully refereed journal ISSN: 2454-132X, Volume-4, Issue-2, April-2018.
Mr.S.Munavvar Hussain, Ms.A.J N Sai Surekha, Ms.D.Archana, Ms.N Hannah Priyanka, “An FPGA Implementation of Health Monitoring System Using IOT” published in International Journal of Creative Research Thoughts (IJCRT), UGC Refereed, Peer and Indexed Journal with ISSN: 2320-2882, Volume-6, Issue-2, April-2018.
Mr.Kishore Vennela, Ms.M.K.Ravali, Ms.G.Manisha, Ms.T.Hema Rani,“An FPGA based Cyclic Navigation Algorithm for Mobile Robots in the Indoor Environment” published in International Journal of Advanced Research, Ideas and Innovations in Technology (IJARIIT), Peer Reviewed Journal with scholarly online, open access, peer-reviewed and fully refereed journal ISSN: 2454-132X, Volume-4, Issue-2, April-2018.
Mr.K.Rambabu, Mr.S.Sanjay, Ms.D.Chupernechitha, Ms.Ch.Pooja, “Monitoring and Controlling of Fire Fighting Robot using IOT” published in International Conference on Innovative Research in Engineering, Science, Management and Humanities (ICIRESMH) at The Institution of Engineers India (IEI) on 18th March-2018.
Mr.Mudasar Basha, Ms.P.Archana, Ms.J.Sandhya, Ms.P.Mounika, “Involuntarily Regulated Car Parking Technique” published in International Journal of Electronics, Electrical and Computational system (IJEECS), Peer Reviewed international journal with ISSN 2348-117X, Volume-7, Issue-4, April-2018.
Mrs.G.Divyavani, Ms.G.Urmila, Ms.M.Swathi, Ms.N.Rithika, “DLAU: A Scalable Deep Learning Accelerator Unit” published in International Journal of Creative Research Thoughts (IJCRT), UGC Refereed, Peer and Indexed Journal with ISSN: 2320-2882, Volume-6, Issue-2, April-2018.
FPGA Implementation of Branch and remove algorithm for mobile robots in indoor environment,during International Conference on Micro Electronics, Electromagnetics and Telecommunications (ICMEET-2017) springer,9th &10th september,2017 by M.C.CHINNAIAH,KISHORE VENNELA,SANJAY DUBEY,T.SATHYA SAVITHRI
Fuzzy Logic based Speech Recognition and Gender classification ,during International Conference on Micro Electronics, Electromagnetics and Telecommunications (ICMEET-2017) springer,9th &10th september,2017 by Dr.Sanjay Dubey,Dr.M.C.Chinnaiah,R.Abhilash
A Versatile Autonomous Navigation Algorithm For Smart Indoor Environment using FPGA based robot,during IEEE Conference ICICICT-2017,7th & 8th JULY ,2017 by M.C.CHINNAIAH,SANJAY DUBEY,P.RAJESH KUMAR,K.ANUSHA,T.SATHYA SAVITHRI
A New approach: An FPGA based Robot Navigation for Patrolling in Service Environment
A Versatile Assistive Device for ADHD with speech Therapy using Embedded System.
Hardware Implementation Of A* Algorithm Shortest Path Algorithm E. Bharat Babu, V.Manideep,t .Lakshmi Manogna,v.Geethasri,hari Krishna
Implementation Of D* Algorithm -Shortest Path Algorithm E.Bharat Babu , M. Andalu , A.Bala Lavanya , P.Manoj Kumar
Reversible Data Hiding in Colour Images Using AES Data Encryption System in Spatial Domain K. Mounika , G. Nandini , K. Prasanna Laxmi , M. Ravindra Bharathi , Mr. E. Bharat Babu, Mr. M. C. Chinnaiah
Bus Identification Module For Visually Impaired M.P.S.N. Mounika , G. Suma , D. Indraja , E. Bharat Babu , M. C. Chinnaiah
Tongue Controlled Wheelchair and Switching of Electrical Appliances For Paralyzed B. Mallika, K. Mounika , M. Mounika , V. Murali Krishna , K. Rambabu , M.C.Chinnaiah
Face Recognition and Detection for Attendance Application B.Manohar Reddy , M. Naveen Kumar , A. Prashanth Reddy , A. Ravi Teja , K. Rambabu , M.C.Chinnaiah
Heart Rate Monitoring System Using Lab View S. Tony Manasa , Y. Sneha , Sajeeda Sultana , V. Srija , S. Munavvar Hussain , M.C. Chinnaiah
Rash Driving Autonomous Control and Vehicle Security System Chukka Sajani , D. Ashwini , M. Jyothi , S. Munavvar Hussain , M. C. Chinnaiah
Eye Camera R. Sai Sneha , Sk.M.Subhani , K. Naveen , B. Ravikumar , V. Santhosh Kumar, M. C. Chinnaiah
Measurement and analysis of human stress using virtual instrumentation Navya.J, G.Navya Sai Vineetha, L.Ramya Raj, V. Santhosh Kumar

Projects - 2017-18

Application:Robot Navigation in indoor environment, Car Parking, Health Monitoring, Industrial Applications

Batch No Name of the Student Project Title Guide
VA0001 B.Bharath Reddy, M.Divya, A.Swapna, Sai Charan Reddy.V Design and Development of hardware scheme for deliberation of curvature type obstacle using FPGA based robot Dr.M.C.Chinnaiah
VA0002 M K Ravali, G. Manisha, T. Hema Rani, B.Sai Charan Rathod An FPGA Based Cyclic Navigation Algorithm For Mobile Robots In An Indoor Environment Mr. Kishore Vennela
VA0003 P. Akshitha, K. Mounika, Javeria Azain An FPGA Based Snake Robot Mr. Mudasar Basha
VA0004 S.B. Arya, R.Neeraja, M.Neeraj Implementation of Pick and place Robot Dr.Sanjay Dubey
VA0005 P Archana, J Sandhya, P.Mounika, D.Ruchitha Involuntarily Regulated Car Parking Technique Mr.Mudasar Basha
VA0006 D.Chupernechitha, S.Sanjay, CH. Pooja Monitoring & Controlling of Fire Fighting Robot using IOT Mr. K Rambabu
VA0007 Archana.D, Sai Surekha A.J.N., N.Hannah Priyanka Health monitoring system using FPGA Mr.S.Munavvar Hussain
VA0008 N.Rithika, M.Swathi,G.Urmila DLAU:A Scalable deep learning accelerator unit Mrs.Divyavani

Mini Projects - 2017-18

Batch No Name of the Student Project Title Guide
Batch 1 K.Prashanth, I.VENIKA SUSHMA, M.monica reddy Design of Embedded based speculum for diagnostic hysteroscopy Dr.M.C.Chinnaiah
Batch 2 CH.PRATYUSHA, PRAVALLIKA, SANDHYA, PRASHANTH TO DEVELOP TAMPER PROOF/FOOL PROOF TECHNOLOGIES TO PREVENT REPROCESSING OF SINGLE-USE (DISPOSABLE) MEDICAL DEVICES Dr.M.C.Chinnaiah
Batch 3 L.Sree Chaitanya,K.Thanuja,K.Harika online inspection of sachets,smart tools integration with iot Mr. Vasudeva Reddy
Batch 4 N,SRI DEVI, P.CHANDANA, CH.PRATYUSHA Solar panel cleaning Mr. Kishore Vennela

Center for VLSI Design

Faculty Coordinator:Mr. K. Madhava Rao

Faculty Members:U.Gnaneshwara Chary,  Ananda Kumar, Ramesh Reddy, Yeshwanth

Major Hardware / EDA Tools

S.No Major Hardware / Software
1 >SYNOPSYS TOOLS
2 XILINX ISE 14.4
3 XUPV5-LX110T BOARD
4 SPARTAN 3A XC3SD1800 DSP STARTAN KIT
5 SPARTAN2 XC2S100 FPGA

SERVER

S.No Major Hardware / Software
6 POWERED BY LINUX SERVER
7 HP PROLIAN ML 150 G5 SERVER,QUAD- CORE INTEL XEON
8 HP 19 “ TFT MONITOR

NETWORK CONNECTION NODES

9 HP DX 2480 DESKTOPS
10 INTEL PENTIUM CORE2 DUO E4600
11 1 GB RAM PX976,320 GB HDD, HP DVD RW
12 969 SATA KEY BOARD /MOUSE, 19”TFT MONITORS

DATA SWITCH

13 10/100 FAST ETHERNET SWITCH 24 PORTS
14 D-LINK DES-1024D

ELECTRICAL EQUIPMENT

15 10 KVA UPS HALF AN HOUR BACKUP

. This Lab exposes the students to latest in IC Design Technology. The main objective of the center is to enabling the excellence in training for VLSI Technology and to bridge the gap between academic and VLSI industry.

CVD-Workshops

S.No Details of the Workshop Details of Resource Persons ( In-house/Industry) Time Duration Academic Year No. of Students Benefited
1 Design For Testability, Industrial Practices Mr. I. B. K. Raju, DFT Engineer, Sankalp Semiconductor Pvt.Ltd. Bangalore. S1: 28-12-19 , S2: 10-01-2020, S3: 25-01-2020, S4: 01-02-2020 2019-20 40
2 Asic Design Using Synopsys Tools Mr. Praveen Kumar- Application Engineer, A.S. Varun- Regional Manager. 14th- 19th OCT-2019 2019-20 30
3 Advanced Digital Design using Verilog HDL Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad 17th to 20th and 22nd December 2018 2018-19 30
4 Advanced Digital Design using Verilog HDL Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad 20-23rd July 2017 at BVRIT, Narsapur. 2017-18 33
5 Introduction to UMA Processor and Simulator Mr. Rajasekhar, Mr. Usha Kiran 10-01-2017 to 13-01-2017. 2016-17 13
5 VLSI Design Flow using SYNOPSYS Tools SYNOPSYS, Hyd and EIGEN Technologies, New Delhi 29th December 2015 -2nd January 2016 2015-16 30
6 VLSI & Embedded Design Flow using XILINX ZYNQ SOC XILINX,Hyd, Coreel Technologyes, Hyd, IEEE, Hyd 9th-11th March 2015 2015-16 30

Guest Lectures

S.No Title of the project Details of Resource Persons ( In-house/Industry) Time Duration Academic Year No. of Students Benefited
1 Dynamic and Static Timing Analysis Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 08/07/2020 2019-20 36
2 Metastability in Front end design Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 11/07/2020 2019-20 36
3 Metastability in Front end design, cont.... Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 18/07/2020 2019-20 36
4 Clock Domain Crossing Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/07/2020 2019-20 36
5 Static Timing Analysis Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/06/2020 2019-20 36
6 Digital Synthesis Flow in VLSI Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/06/2020 2019-20 36
7 Digital Synthesis Flow with Low Power in VLSI( Five day STTP on Low Power VLSI) Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/06/2020 2019-20 36
8 Industry approach for VLSI Front End Design Problem Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 27/06/2020 2019-20 36
9 Polymorphism Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 03/03/2020 2019-20 36
10 Randomizing Objects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 07/03/2020 2019-20 36
11 Random Variables Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 14/03/2020 2019-20 36
12 Industrial approach in front end design Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 22/05/2020 2019-20 36
13 OOPS concept in System verilog Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 04/02/2020 2019-20 36
14 Class, Object Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 15/02/2020 2019-20 36
15 Inheritance, Abstraction Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/02/2020 2019-20 36
16 Encapsulation Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/01/2020 2019-20 36
17 Verification Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 04/01/2020 2019-20 36
18 Introduction to System Verilog Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 10/01/2020 2019-20 36
19 Data Types Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 23/01/2020 2019-20 36
20 Arrays Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/01/2020 2019-20 36
21 Synthesis Flow Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 07/12/2019 2019-20 36
22 Static Timing Analysis using Prime Time Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 11/12/2019 2019-20 36
23 Functional/Gate Simulation and Verification Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/12/2019 2019-20 36
24 Physical Verification and Extraction. Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 28/12/2019 2019-20 36
25 M.Tech Projects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 26/04/2018 2017-18 11
26 M.Tech Projects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 19/04/2018 2017-18 11
27 Verilog Constructs Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/04/2018 2017-18 22
28 Verilog Programming Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 06/04/2018 2017-18 71
29 B.Tech and M.Tech Project Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 31/03/2018 2017-18 45
30 Interaction with M.Tech Students Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 24/03/2018 2017-18 14
31 Verilog Concepts discussion with II-ECE-B Students Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 09/03/2018 2017-18 71
32 Verilog Programming and Test Benches Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 03/03/2018 2017-18 26
33 Workshop on ASIC Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 23/02/2018 2017-18 52
34 Workshop on ASIC Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 17/02/2018 2017-18 52
35 FPGA Architectures Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 10/02/2018 2017-18 38
36 FPGA Design Flow Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 06/02/2018 2017-18 26
37 Finite State Machines Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/01/2018 2017-18 26

Participation in contests by Students

S.No Name of the Contest Place No. of Students Academic Year
1 Sankalp Hackathon Admas University,Kolkata 2 2019-20
2 L& T Techgium Bangalore 2 2019-20
3 NASA Space App Challenge New Delhi 2 2019-20
4 DST & Texas Instruments India Innovation Challenge Design Contest 2018 IIM, Bangalore 4 2018-19
5 Startup India MHRD, Hyderabad 2 2018-19
6 Synopsys India 2017 Custom Design Contest Synopsys India Pvt. Ltd., Uttar Pradesh 2 2017-18
7 Synopsys India 2016 Custom Design Contest Synopsys India Pvt. Ltd., Uttar Pradesh 2 2016-17

Certifications done by Students

S.No Certificate from Number of Students Certified
1 Amazon Web Services 1
2 Cisco 1
3 CITD, Hyd 9
4 Cognitive class 5
5 Coursera 87
6 Google 1
7 Guvi 1
8 HackerRank 1
9 ICSI 1
10 Jigsaw 5
11 Mentor Graphics 6
12 NASSCOM 3
13 NEO Organization 1
14 NPTEL 5
15 PIRPLE 1
16 Simplilearn 13
17 Tata Steel 1
18 TCS 3
19 Udemy 3

Placements in Core Industries

S.No Roll Number Name of the Student Company Placed Academic Year
1 16211A0403 Himavanth SilinConch

2019-20

 

2 16211A0405 Ramsai Reddy VEDA IIT
3 16211A0456 Prathibha VEDA IIT
4 16211A04N3 Sandeep VEDA IIT
5 16211A0401 Rakesh HYSOC Technologies
6 16211A0405 Ram Sai Reddy HYSOC Technologies
7 16211A04B4 Jyotsna HYSOC Technologies
8 16211A04M9 Mahesh Babu HYSOC Technologies
9 17211D5703 Ismat Amreena Juntran
10 17211D5711 Gopa Sowmya Juntran
11 17211D5706 Prashamsa SiliConch
12 15211A04F4 JAYENDRA PRASAD HYSOC Technologies 2018-19
13 15211A04G6 R TEJASWINI HYSOC Technologies
14 15211A0437 PRASHANTH KUMAR HYSOC Technologies
15 15211A04H2 P GOUTHAM HYSOC Technologies
16 15211A0498 SAI RAM PRAKASH HYSOC Technologies
17 16215A0417 USHA RANI HYSOC Technologies
18 15211A04F4 JAYENDRA PRASAD SOCTRONICS (VEDA IIT)
19 15211A0494 PRASHANTH KUMAR SOCTRONICS (VEDA IIT)
20 15211A04H2 P GOUTHAM SOCTRONICS (VEDA IIT)
21 15215A0403 HIMAVANTH Ferventz Semi-Conductors
22 15211A0410 ARSHIVA Ferventz Semi-Conductors
23 15215A0416 PRAVALLIKA Ferventz Semi-Conductors
24 15211A04E2 SRI DEVI Ferventz Semi-Conductors
25 15211A04E7 ASHRITH Ferventz Semi-Conductors
26 15211A04G0 CHANDANA Ferventz Semi-Conductors
27 15215A0443 DIWAKAR Ferventz Semi-Conductors
28 15215A0423 SHIVA PRASAD HYSOC Technologies 2017-18
29 14211A0487 CHANDANA HYSOC Technologies
30 14211A04H9 TEJASWINI HYSOC Technologies
31 14211A0429 SRUJAN HYSOC Technologies
32 14211A04D2 P SHRUTHI HYSOC Technologies
33 14211A04D5 SAI BHAVYA HYSOC Technologies
34 14211A0447 VYSHNAVI SOCTRONICS (VEDA IIT)
35 14211A0474 NAGA SRUJANA SOCTRONICS (VEDA IIT)
36 14211A04C6 SHARATH CHANDRA SOCTRONICS (VEDA IIT)
37 14211A0466 Hari Hara Naga Vamshi SOCTRONICS (VEDA IIT)
38 14211A0470 TRIPURA ADEPT CHIPS
39 14211A04E7 HARI TEJA ADEPT CHIPS
40 14211A0466 Hari Hara Naga Vamshi ADEPT CHIPS
41 14211A0421 MAHITHA ADEPT CHIPS
42 14211A04C4 GOPAL ADEPT CHIPS
43 14211A04F7 KRANTHI KUMAR ADEPT CHIPS
44 13211A0469 Manasa Sarovari VEDA IIT 2016-17
45 13211A04G6 Venkata Kishore Adept Chips
46 13211A0492 PremChand Adept Chips
47 14215A0433 Anil Kumar Adept Chips

Internships in Core Industries

S.No Roll Number Name of the Student Company Placed Academic Year
1 16211A04F7 Shailu HYSOC Technologies 2019-20
2 16211A0456 Pratibha HYSOC Technologies
3 16211A04E0 Sree Vidya HYSOC Technologies
4 16211A04G6 Naresh HYSOC Technologies
5 16211A0483 Rakesh K HYSOC Technologies
6 16211A0466 Sushmitha HYSOC Technologies
7 12211AD4 Shyam Sunder Reddy CYIENT, Hyd 2015-16
8 12211AD6 Siddartha Reddy CYIENT, Hyd
9 12211AC6 Sangameshwar CYIENT, Hyd
10 14211D5706 (M.Tech) B.Malathi Research Center Imarat (RCI) ,Hyderabad
11 14211D5713 (M.Tech) P.Shyamala Research Center Imarat (RCI) ,Hyderabad
12 14211D5710 (M.Tech) Sheri Mounika Smarttrak, Hyderabad
13 14211D5720 (M.Tech) T.Vishwa Tevatyron Technology, Noida
14 14211D5707 (M.Tech) R.Manikanta Manjeera Digital Systems
15 14211D5717 (M.Tech) Sushanth Reddy Manjeera Digital Systems
16 13211D5704 (M.Tech) Kavya Paruchuri Synopsys
17 13211D5708 (M.Tech) G.Abhishek Synopsys
18 13211D5709 (M.Tech) K.Akhila Synopsys
19 13211D5715 (M.Tech) M.Harish Kumar Synopsys
20 13211D5719 (M.Tech) Sai Kriranmayee Synopsys
21 11211A04A3 Kotha Rajesh Synopsys

Student - Faculty Publications 2019-20

U.Gnaneshwara chary, Poralla Divya, The International Journal of Analytical and Experimental Model Analysis “June 2020 Volume XII, issue VI, Pg. nos:1404-1410 Design and Implementation of VLSI architecture for Error correction and Detection.
U.Gnaneshwara chary, Goundla Priyanka The International Journal of Analytical and Experimental Model Analysis June 2020Vol ume XII, issue VI, Pg. nos:1388-1394 Low Quantum Cost Reversible Logic Gates and QCA Architectures. >
K.Madhava Rao,P. Rajesh, P. Akash, P.Pragath & M. Sai Mahesh The International Journal of Analytical and Experimental Model Analysis April-2020 volume XII,issue IV, Pg.nos :1957-1963 FPGA Based Robotic ARM Controller.
K.Madhava Rao, D. Sai Shradha, Ch. Kavya Madhuri, B. Ravi, D. SudheerInternational Journal of Research in Engineering, Science and Management April-2020 Volume 4, Issue 3, Pg.nos: 332-334 Implementation of ALU by Vedic Algorithm.
K.Madava Rao, International Journal of Recent Technology and Engineering (IJRTE) Jan-20 ISSN: 2277-3878, Volume-8, Issue-5,Design of FinFET based 128 bit SRAM in 7nm & various Effects near threshold operation for ultra low power application. Estimation in Connected Cars (SCOPUS).
T.Vasudeva Reddy, K.Madava Rao, P.Kavitha Reddy International Journal of Innovative Technology and Exploring Engineering (IJITEE) Dec-19 ISSN: 2278-3075, Volume-9 Issue-2, MEMS Design Techniques and Performance (SCOPUS).
C Ramesh Kumar Reddy, Syed Muqtar Nawaz, Sureddy Sravya, Mohammed Imran International Journal of Advance Research, Ideas and Innovations in Technology May 2020 ISSN: 2454-132X Impact factor: 6.078 Volume 6, issue 2 ASIC implementation of smart home using VLSI design.
J. Yeshwanth Reddy International Journal of Current Advanced ResearchApril-2020 Volume : 9 , Issue : 4 Implementation of I2C communication protocol with RTC and EPROM using FPFA.

Student - Faculty Publications 2018-19

A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic- U. G. Chary, Bala Bandhavi, Naga srujana, Tripura..
GESTURE BASED HOME AUTOMATION SYSTEM USING SPARTAN 3A, ASIC International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 Scopus, K. Madhava Rao.
Dr. T.Vasudeva Reddy & K.MadhavaRao has presented a paper on "Novel strategies of Low power Subthreshold SRAM designs under 32nm for real-time applications." in InternationalConference on Computational and Intelligent Techniques for Automation of Engineering Systems (CITAES), Scopus Nov 30Th&1st December
Clock feed through problem reduction- U. Gnaneshwara chary, I.B.K Raju, Yeshwanth Reddy.
Design of parity generator and parity checker using QCA- U.G.Chary.
U-Turn Collision Caution System Using FPGA-(conference paper), U.Gnaneshwara chary, Tejaswini, Vishnavi Manda, Sharath Kumar..
K. Madhava Rao has presented a paper on “Performance & functionality of novel Subthreshold SRAM’s using low power techniques for SoC designs”in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 15th & 16th,,October 2018,Coimbatore,india.
K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018 ,Mysore,India.
K. Madhava Rao, et al published paper on “Design, Simulation & Comparison Of Novel Tg8t SRAM With Traditional SRAM Design In Open Access International Journal Of Science & Engineering, Volume 2,Issuexii,December 2018||ISSN (Online) 2456-3293.(UGC approved)
Udari Gnaneshwara chary, J. Yeshwanth Reddy published a paper on Analysis of Clockfeedthrough and Chargeinjection using cadence 180nm Technology in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)
Udari Gnaneshwara chary published a paper on A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)
Dr T. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018,Mysore,India

Student - Faculty Publications 2017-18

K. Madhava Rao, et al published paper on “Design & comparison of novel low power, sub threshold Schmitt trigger based SRAM & source coupled logic for cognitive applications. In Open Access International Journal of Science & Engineering, Volume 2, Issue , November 2017||ISSN (Online) 2456-3293.
K. Madhava Rao, et al published paper on “Design & Analysis of Single Bit Sub-Threshold SRAM using Traditional SRAM Design under 32nm Design” Volume 5, Issue XI, November 2017,in International Journal for Research in Applied Science & Engineering Technology.

BVRIT - Cyient Incubation Centre

Objective of this center is to create academic center of excellence in semiconductor technology. The key activities of the above center is to provide domain training by VLSI experts from CYIENT to students supported by two faculty members Mr.I.B.K Raju and U. Gnaneshwara chary from Dept of Electronics and communication, BVRIT who also got trained by CYIENT. Training is followed by Identify the real time problems and finding the technological solutions and validating the idea (proof of concept). Once the idea is formulated and validated design and implementation will be proceeded.

BATCH-II

TRAINING PHASE

Details of the Training Details of Resource Persons Date & Time Duration No. of Students Benefited Remarks
 6-Months Hands on Training Program on VLSI Design         CYIENT Industrial Experts:  18/07/16 to 31/12/16          24 UG Students          Completed Successfully        
Avinash Yedlapati, Project Manager
Mandeep Singh, Project Lead
Vineeth Tandon, Assistant Project Manager
Prasad Raju, Assistant Project Manager
Lingaiah Bontha, Team Lead
Vinay, Associate Engineer
BVRITN Academic Experts:
I.B.K.Raju, Assoc Prof, ECE Dept
U.Gnaneshwara Chary, Asst Prof, ECE Dept

PROJECT PHASE

Details of the Activity Title of Project Date & Time Duration No. of Students Benefited Remarks
Ideation & Brain Storming ASIC Implementation of NAND Flash Controller 1/3/16 to 31/3/16 21 (17 UG+4 PG) Completed Successfully
RTL Design ASIC Implementation of NAND Flash Controller 4/7/2016 to 30/9/2016 21 (17 UG+4 PG) Completed Successfully
RTL Verification ASIC Implementation of NAND Flash Controller 1/10/2016 21 (17 UG+4 PG) Completed Successfully

TRAINING PHASE

Faculty Training

Training Details: 4-Month Faculty Training Program
Dates: 2/11/15 to 29/2/16
Venue CYIENT Ltd ,Hyd
No. of Students Benefited: 2 (I.B.K.Raju, Assoc Prof & U.Gnaneshwara Chary, Asst Prof )
Status of Training sessions: Completed Successfully

Student Training

Training Details: 3-Months Hands on Training Program on VLSI Design
Dates: 2/12/15 to 29/2/16
No. of Students Benefited: 21 (17 UG+4 PG)
Status of Training sessions: Completed Successfully

Training Details

Date Topics covered Resource Persons
02/12/2015 ASIC/FPGA Design Flow Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
03/12/2015 to 05/12/2015 Exercises on Digital and Advanced Digital Designs I.B.K. Raju &Gnaneshwara chary
07/12/2015 FSM Design Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
09/12/2015 to 12/12/2015 Exercises/Labs on Verilog/State Machines/System Verilog I.B.K. Raju &Gnaneshwara chary
14/12/2015 Verification Mr. Vineet, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
16/12/2015 to 19/12/2015 Exercises/Labs on writing effective Testbenches I.B.K. Raju &Gnaneshwara chary
22/12/2015 to 26/12/2015 Exercises/Labs on RTL Code and Testbenches with Code Coverage options I.B.K. Raju & Gnaneshwara chary
28/12/2015 Synthesis Mr. P. Madhan Mohan,Team Lead, CYIENT, Mr. B.Lingaiah, Team Lead, CYIENT
29/12/2015 to 05/01/2016 Exercises/Labs on Synthesis of Digital Circuits I.B.K. Raju & Gnaneshwara chary
07/01/2016 System Verilog verification Methodology Mr. Vineet, Manager, CYIENT, HYD
20/01/2016 Logic Equivalence Checking & Static Timing Analysis Mr. P. Madhan,Team Lead, CYIENT, Mr. P. Bhargava, Team Lead, CYIENT
21/01/2016 to 23/01/2016 Exercises/Labs on LEC I.B.K. Raju & Gnaneshwara chary
28/1/2016 Physical Design Mr. K.Madhusudan Rao, Project Manager,CYIENT, HYD, Mr. Konda Reddy, Tech lead, CYIENT, HYD
04/02/2016 Analog Layout Design Mr. Raja Randham, Layout Manager, CYIENT, HYD, Mr. Vishnu, Layout Engineer, CYIENT, HYD