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EAMCET | ICET | ECET | CODE: BVRI

PGECET | CODE: BVRI1 | NIRF

Dr. U. Gnaneshwara Chary

Dr. U. Gnaneshwara Chary

Assistant Professor, ECE Dept.
Gnaneshwara.chary@bvrit.ac.in

B.Tech: – Electronics and Communication Engineering – Jatipita College of engineering– 2006
M.Tech: – VLSI -VNR Vignana Jyothi institute of technology – 2010
Ph.D.: -completed Ph.D in K L University, Vijayawada,

Teaching Experience – 20 Years

JNTU Registration No – 86150402-165539
BVRIT ID – 507
Ratification Status – Ratified

AICTE Registration ID: 1-1485326039

Scopus ID: 57202074535

Google Scholar: https://scholar.google.com/scholar?hl=en&as_sdt=0%2C5&q=gnaneshwara+chary&btnG=

LinkedIn: https://www.linkedin.com/in/dr-gnaneshwara-chary-udari-05577176/

  1. Analog VLSI Design
  2. Low Power VLSI Design
  3. Advanced IC Packaging
  4. Quantum Computing
  5. Quantum Semiconductors
  1. CMOS ANALOG VLSI DESIGN
  1. IEEE Membership – (ID: 96509154)
  2.  CSI Membership – (ID: 5021240047).
  3. IESA
  1. M.Tech (VLSI Systems Design) coordinator.
  2. Lab Coordinator “Center for VLSI design”.
  3. VLSI Core Placement Trainer.
  4. PG (VLSI) Project Coordinator.
  1. Completed Quantum Computing and Programming training and Quantum Program titled Quantum Solvers – Algorithms for the World’s Hardest Problems by Womanium, QWorld & Wiser 2025.
  2. Completed QT-03 Basic Quantum Programming Course jointly organised by IIT Kanpur, IIT Roorkee, IIT Guwahati, MNIT Jaipur, NIT Warangal and IIITDM Jabalpur.
  3. Completed a course on Quantum Computing with Merit jointly organized by IIT Roorkee and C-DAC Hyderabad with the support of the Ministry of Electronics and Information Technology, Government of India from 3rd- 25th May 2025.
  4. Completed QT-02 Foundations of Quantum Technologies course jointly organised by IIT Kanpur, IIT Roorkee, IIT Guwahati, MNIT Jaipur, NIT Warangal and IIITDM Jabalpur.
  5. Completed NPTEL Course on Digital Electronics.
  1. M.Tech. guidance: Guided 15 students
  2. B.Tech. project guidance: Guided more than 25 students
  3. No. of international journal & international conference publications: 13
  • Participated in a two-week Online Faculty Development Programme on “RISC-V VLSI Implementation Flow: RTL2GDS” jointly organised by Electronics and ICT Academies held from 27 March – 10 April, 2021 under the “Scheme of financial assistance for setting up of Electronics and ICT Academies” of the Ministry of Electronics and Information Technology (MeitY), Government of India.
  • Attended a AICTE Training And Learning (ATAL) Academy Online Elementary FDP on “Quantum Computing and Quantum Cryptography” from 2021-6-7 to 2021-6-11 at National Institute of Technology Karnataka.
  • Attended a Workshop on Design of Experiments(DOE) Held at VEDIC,AZIZNAGAR, on 20th February,2020. Attended a three days hands on Workshop on “Progression Workshop” Held at VEDIC,AZIZNAGAR, on 14th November,2019.
  • Attended a Workshop on “Progression Workshop” Held at VEDIC,AZIZNAGAR, on 14th November,2019.
  • Attended a Workshop on Unconcious Bias In the Workplace Held at VEDIC,AZIZNAGAR, on 4th February,2019.
  • Attended a Workshop on Unconcious Bias In the Workplace Held at VEDIC,AZIZNAGAR, on 8th March,2019.
  • Attended a Workshop on “Inspire Impact Introspect ” Held at VEDIC,AZIZNAGAR, on 17th to 19th September, 2018.
  • Attended a International conference on Research Advancements in Computer Science and communication ICRACSC-2016 on 29th and 30th Dec,2016.
  • Attended and a IEEE international conference on Devices Circuits and Systems on 6th to 8th March 2014 at Karunya University, Tamilnadu.
  • Attended a One-Day Faculty Development Programme on intellectual property Rights with an emphasis on patients and copyrights, held on 01-Nov-2014 at BVRIT, Narsapur, Telangana.
  • Attended a 2-Day faculty development programme on Analog circuit Design using Cadence Tools on 4th and 5th January, 2013 at BVRIT.
  • Attended a 3 day workshop on “PLL Theory Design” on 8th Dec 2012, Conducted by VLSI Society of India at CADENCE office, Bangalore.
  • Attended a 42nd ISTE annual convention at ANURAG group of Institutions on 20th to 22nd December, 2012.
  • Attended a complementary seminar on MATLAB and Simulink for Engineering Education on 31/08/2012 at Hyderabad
  • Attended IEEE sponsored workshop on Programmable SOCs and Applications on 30th November 2010 at BVRIT, Narsapur.
  1. Organized a 6-day Faculty Development Program on Unlocking the Potential of AI in VLSI System Design and IC Packaging in semiconductor from 16th December 2024 to 21st December 2024.
  1. Gnaneshwara Chary, et al. “Device-to-device data transmission over sound waves using FSK/BPSK/QPSK.” Communication, Software and Networks: Proceedings of INDIA 2022. Singapore: Springer Nature Singapore, 2022. 95-102.(Scopus Indexed)
  2. Ganeshwara Chary, et al. “Design of peripheral component interconnect express physical layer.” Recent Trends in VLSI and Semiconductor Packaging. CRC Press 595-603. (Scopus Indexed)
  3. Gnaneshwara Chary, et al. “Performance of a Low-Power 6T-SRAM Cell for Energy-Efficient Leakage Reduction Using DTMOS Technique.” Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems: ICCCES 2022. Singapore: Springer Nature Singapore, 2023.(Scopus Indexed)
  4. Gnaneshwara Chary Udari. “Design and implementation of low quantum cost reversible universal shift register.” 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT). IEEE, 2023. (Scopus Indexed)
  5. Gnaneshwara Chary Udari. “An efficient reversible universal shift register with minimal quantum cost.” 2023 IEEE Women in Technology Conference (WINTECHCON). IEEE, 2023.(Scopus Indexed)
  6. Gnaneshwara Chary et al. “A Review paper on Optimized Reconfigurable Cell Array.” 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2021
  7. Udari Gnaneshwara Chary “Area Optimised Efficient Multiplication Using Modified Round Square Approximation.” In 2023 IEEE International Conference on Integrated Circuits and Communication Systems (ICICACS), pp. 1-5. IEEE, 2023.
  8. Udari Gnaneshwara Chary “Design of Image Kernels using Reversible Logic Gates: Enhancing Image with Information-Preserving Operations.” In 2024 International Conference on Expert Clouds and Applications (ICOECA), pp. 851-859. IEEE, 2024.(Scopus Indexed)
  9. Udari Gnaneshwara Chary . “Low power analog multiplexers for ECG applications.” Journal of Physics: Conference Series. Vol. 1804. No. 1. IOP Publishing, 2021.(Scopus Indexed)
  10. Udari Gnaneshwara Chary”An architectural design approach of AES using MAC-AES algorithm for reduced delay.” In AIP Conference Proceedings, vol. 3157, no. 1, p. 070003. AIP Publishing LLC, 2025.(Scopus Indexed)
  11. Gnaneshwara Chary Udari. “Quantum Error Correction: Overcoming the Fragility of Qubits for Reliable Quantum Computing.” In Exploring the Fusion of Quantum Computing and Machine Learning, pp. 107-130. IGI Global Scientific Publishing, 2025.(Scopus Indexed)
  1. Udari Gnaneshwara Chary, and Kakarla Hari Kishore. “Low Voltage and Low Power Front Panel Design for 12 Lead ECG.” IEEE Access10 (2022): 69455-69461.(SCI & Scopus & WoS Indexed)
  2. Udari Gnaneshwara Chary, Swathi Mummadi, and Kakarla Hari Kishore. “Optimization of two-stage DTMOS operational transconductance amplifier with Firefly algorithm.” Optimization3 (2025).(Scopus Indexed)
  3. Udari Gnaneshwara Chary, and Kakarla Hari Kishore. “HSPICE simulation and analysis of current reused operational transconductance amplifiers for biomedical applications.” International Journal of Electrical and Computer Engineering (IJECE)1 (2025): 196-207.(Scopus Indexed)
  4. Gnaneshwara Chary Udari, and Sanjeeva Reddy B. Rama. “Performance Evaluation of RISC-V Microcontroller System on FPGA: A Study of the NEORV32 Core.” International Journal of Integrated Engineering16, no. 1 (2024): 312-317.
  5. Udari Gnaneshwara Chary “Low power 16-channel data selector for bio-medical applications.” International Journal of VLSI Design & Communication Systems6 (2014): 9.(UGC care Indexed)
  6. Gnaneshwara Chary. “LabVIEW controlled antenna positioner.” (2020).
  7. Udary Gnaneshwara Chary. “Design and Modeling of Schmitt Trigger-based Sub-Threshold 8T SRAM for Low Power Applications.” International Journal of Computer Applications 104.12 (2014).
  1. Gnaneshwara Chary Udari (2025), ”Quantum error correction: Overcoming the fragility of qubits for reliable quantum computing” in Exploring the Fusion of Quantum Computing and Machine Learning. IGI Global, Pages: 107 – 129. DOI: 10.4018/979-8-3693-6225-9.ch005 (Scopus Indexed)
  2. Gnaneshwara Chary Udari, C. Achyuth, C. Karthik (2025), ”Error Correction Methods for Protecting Quantum Information” The Quantum AI Era of Neuromarketing. IGI Global, Pages: 113-132. DOI: 10.4018/979-8-3693-7673-7.ch005 (Scopus Indexed)
  1. Mummadi Swathi et al. titled ”Dynamic Qubit Interconnect Routing System for Reduc ing Inter-Qubit Error Rates in VLSI Quantum Architectures” published in 2024. Patent Application Number: 202441084951. (Published)
  2. Udari Gnaneshwara Chary. et al. titled ”Implementation of Alert System Device(ASD) for The Avoidance of Accidents at Curve Prone Areas” published in 2022. Patent Application Number: 202041057198. (Published)
  1. Serving as a Visiting Research fellow at University of Malaysia, Perlis(UNIMAP) in 2024-25 & 2025-26.
  2. Received Certificate of Achievement from Pennylane, Wiser, Womanium and Qworld, 2025.
  3. Received Quantum certificates for the Quantum Courses, organized by MNIT Jaipur, NIT Patna, IIT Kanpur, IIT Roorkee, IIT Guwahati, IIITDM Jabalpur, NIT Warangal.
  4. Completed INAE – CEEEP course from IIT Delhi.

CI – Chief Investigator for C2S-Chip to startup Program sponsored Synopsys, Cadence, Mentor and Xilinx tools 60+ users.

  1. Reviewer for IEEE ACCESS (SCIE & Scopus Indexed) – Reviewed 5+ manuscripts till date
  2. Reviewer for IEEE SMART conference 2025 (Taylor & Francis)

Key Role in

  • Industry interactions done with BITSILICA, AMD,INTEL, MIRAFRA,INFOSYS, MICRON, GRAPHINE Semiconductors, ADEPTCHIPS, DHRUVASPACE, NIAR, JAY ROBOTICS,XILINX, FERVENTZ Semiconductors.
  • MOU between Dhruva Space and BVRIT in Dec 2019: With the effect of this MOU Dhruva space established a space Lab at BVRIT.
  • Establishment of HAM LAB in the Department of ECE in 2018.
  • MOU between Ferventz Semiconductors and BVRIT in 2018: With the effect of this total 9 students are placed in Ferventz semiconductors.
  • MOU between HySoC and BVRIT in 2017: With the effect of this total 16 students are placed in Hysoc within two years.
  • Establishing BVRIT- CYIENT Incubation Centre at BVRIT in 2016 : Here Projects are developed from RTL to GDS-II level.
  • MOU between SYNOPSYS and BVRIT: Under the university program SYNOPSYS conducting workshops at BVRIT and 10 students are got placement in SYNOPSYS Hyderabad and Bangalore.
  • MOU between CYIENT and BVRIT: 12 students are joined as interns in the CYIENT for one year in Verification division.
  1. Successfully delivered RTL IP consultancy Project to BITSILICA 2024-Rs.50000/-.
  2. Ongoing verification consultancy project with Qubitsemi- Rs.50000/-.
  3. Ongoing AI-based FPGA project with Swansorters Solutions, Bangalore – 10,00,000/-.

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