B.Tech: – Electronics and Communication Engineering – Jatipita College of engineering– 2006
M.Tech: – VLSI -VNR Vignana Jyothi institute of technology – 2010
Ph.D.: – pursuing in CMOS analog IC design for Biomedical Applications from JNTUH
Teaching Experience – 12 Years
JNTU Registration No – 86150402-165539
BVRIT ID – 507
Ratification Status – Ratified
- HAM LAB coordinator.
- M.Tech (VLSI Systems Design) coordinator.
- Team member in “Center for VLSI design”.
- VLSI Core Placement Trainer.
- PG (VLSI) Project Coordinator.
- Certified by NPTEL in the course Digital Logic Design
- Certification in Restricted Grade HAM License.
- Coursera Certification in Introduction to Quantum computing from St.Petersberg university.
- Coursera Certification in Introduction to Quantum Physics from St.Petersberg university.
- Certification in “SYSTEM VERILOG” by CYIENT Ltd.
- Certification in “Technical Entrepreneurship development” by Indian School of Business(ISB).
- M.Tech. guidance: Guided 15 students
- B.Tech. project guidance: Guided more than 25 students
- No. of international journal & international conference publications: 13
- CMOS ANALOG VLSI DESIGN
- CMOS Analog and Digital IC Design
- Quantam Computing
- Attended 5 day STTP Program on “An Emerging Paradigmof Low Power Computational Vlsi Design” at BVRIT from 16th June to 20th June.
- Attended 3 day workshop on “ Digital IC Design with DFT concepts using Mentor Graphics Tools” by Apply volt at MIST, Hyderabad.
- Attended 5 day workshop on “Advanced digital design using verilog” from 17th Dec 2018 to 23rd Dec 2018.
- Mr. Gnaneshwara Chary, “Design and Implementation of VLSI Architecture for Error Detection and Correction “ International Journal of Analytical and Experimental Model of Analysis, June 2020.
- Mr. Gnaneshwara Chary, “Design And Implementation Of Reversible Logic Gates Using 2- Dimentional 4 Dot 2 Electron QCA “ International Journal of Analytical and Experimental Model of Analysis, June 2020.
- Mr. Gnaneshwara Chary, “LabVIEW controlled antenna positioner “ Advance Research, Ideas and Innovations in Technology, June 2020.
- Mr. Gnaneshwara Chary, “Design of parity generator and parity checker using QCA” International Journal of Pure and Applied mathematics 2018 , Volume118 No. 24.
- Mr. Gnaneshwara Chary, “An Efficient VLSI Architecture for Matrix Based RNS Backward Converter”, Elsevier International Conference on Computational Modeling and Security (CMS 2016).
- Mr. Gnaneshwara Chary, ”Parallel Self Timer Adder Using Full Swing GDI”, International Conference on Research Advancements in Computer Science and Communications, December 2016, Narsapur, Telangana.
- Mr.Gnaneshwara Chary “Area-Power Efficient Vedic Multiplier Using Compressors”, Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015, Jan 2015,Visakapatanam, AP
- Mr. Gnaneshwara Chary, Mr. I.B.K Raju, Ms. G. Devi Tejashwini” Ultra-Low Power Circuit Design using Double-Gate Fin FETs “ , International Conference On Devices Circuits And Systems” (ICDCS’14), March 2014 , Coimbatore, T.N.
- Mr. Gnaneshwara Chary” Data Communication Using HDLC Protocol “ , Journal Of Innovative Research In Electrical, Electronics, Instrumentation And Control Engineering Vol. 2, Issue 5, May 2014.
- Mr. Gnaneshwara Chary, ” Design of Low Voltage Low Power Analog Multiplexer for Bio-Medical Application” , International Journal of Engineering and Advanced Technology (IJEAT) Vol. 3, Issue 3,january 2014.
- Mr. Gnaneshwara Chary, ” sub threshold sram design for ultra low power applications” International Journal of Scientific and Engineering Research (IJSER) Vol. 5, Issue 5,may 2014.
- Mr. Gnaneshwara Chary, ” estimation of leakage power in CMOS digital circuit stacks” International Journal Of Technical & Scientific Research -Vol.2, Issue .1, november 2014.
- Mr. Gnaneshwara Chary, ” Design and Modeling of Schmitt Trigger-based Sub-Threshold 8T SRAM for Low Power Applications” ” International Journal Of computer applications -Vol.104, number 12, november 2014.
